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    Semiconductor memory
    1.
    发明授权
    Semiconductor memory 有权
    半导体存储器

    公开(公告)号：US07937645B2

    公开(公告)日：2011-05-03

    申请号：US11443109

    申请日：2006-05-31

    申请人： Toshio Ogawa ,  Yoshihiro Takemae ,  Yoshinori Okajima ,  Tetsuhiko Endo ,  Yasuro Matsuzaki

    发明人： Toshio Ogawa ,  Yoshihiro Takemae ,  Yoshinori Okajima ,  Tetsuhiko Endo ,  Yasuro Matsuzaki

    IPC分类号： G11C29/00

    CPC分类号： G11C29/42

    摘要： A conversion control unit sets a converting function of a write data conversion unit or a read data conversion unit enabled or disabled for each controller. Accordingly, for a controller which needs original external data, the external data can be inputted and outputted, whereas for a controller which needs converted internal data, the internal data can be inputted and outputted. A data converting function of a conventional controller can be realized in a semiconductor memory, which can reduce the load on the controller. As a result, the performance of a system can be improved. A disabled controller which has no access right cannot read correct data (original data before conversion). Hence, the security of data written into the semiconductor memory can be protected.

    摘要翻译： 转换控制单元设置对每个控制器启用或禁用的写数据转换单元或读数据转换单元的转换功能。 因此，对于需要原始外部数据的控制器，可以输入和输出外部数据，而对于需要转换的内部数据的控制器，可以输入和输出内部数据。 可以在半导体存储器中实现传统控制器的数据转换功能，这可以减少控制器上的负载。 结果，可以提高系统的性能。 无权访问的无​​效控制器无法读取正确的数据（转换前的原始数据）。 因此，可以保护写入半导体存储器的数据的安全性。

    Memory system
    3.
    发明授权
    Memory system 有权
    内存系统

    公开(公告)号：US07386659B2

    公开(公告)日：2008-06-10

    申请号：US11505837

    申请日：2006-08-18

    申请人： Yoshihiro Takemae

    发明人： Yoshihiro Takemae

    IPC分类号： G06F13/38

    CPC分类号： G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0688 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0623 ,  G06F13/1694 ,  G06F2212/7201 ,  G11C5/04 ,  G11C7/1072

    摘要： A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

    摘要翻译： 存储器控制器根据要操作的存储器芯片的操作规范，将从控制器输出的控制器输出信号转换为存储器输入信号，并通过公共总线将结果输出到存储器芯片。 存储器控制器还通过公共总线接收从存储器芯片输出的存储器输出信号，并将接收的信号转换成可接收到控制器的控制器输入信号。 这允许单个存储器控制器访问多种类型的存储器芯片。 结果，存储器控制器可以减小芯片尺寸，降低存储器系统的成本。

    Memory system
    4.
    发明授权
    Memory system 有权

    公开(公告)号：US07370141B2

    公开(公告)日：2008-05-06

    申请号：US11505838

    申请日：2006-08-18

    申请人： Yoshihiro Takemae

    发明人： Yoshihiro Takemae

    IPC分类号： G06F13/38

    CPC分类号： G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0688 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0623 ,  G06F13/1694 ,  G06F2212/7201 ,  G11C5/04 ,  G11C7/1072

    摘要： A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

    Memory system
    5.
    发明申请
    Memory system 有权

    公开(公告)号：US20060282608A1

    公开(公告)日：2006-12-14

    申请号：US11505835

    申请日：2006-08-18

    申请人： Yoshihiro Takemae

    发明人： Yoshihiro Takemae

    IPC分类号： G06F12/00

    CPC分类号： G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0688 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0623 ,  G06F13/1694 ,  G06F2212/7201 ,  G11C5/04 ,  G11C7/1072

    摘要： A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

    Semiconductor memory device capable of reducing power consumption in self-refresh operation
    7.
    发明授权
    Semiconductor memory device capable of reducing power consumption in self-refresh operation 有权
    能够降低自刷新操作中的功耗的半导体存储器件

    公开(公告)号：US06215714B1

    公开(公告)日：2001-04-10

    申请号：US09517279

    申请日：2000-03-02

    申请人： Yoshihiro Takemae ,  Yasurou Matsuzaki

    发明人： Yoshihiro Takemae ,  Yasurou Matsuzaki

    IPC分类号： G11C700

    CPC分类号： G11C11/40622 ,  G11C11/406

    摘要： A semiconductor memory device, which refreshes memory cells to retain data, has a first refresh mode and a second refresh mode. The first refresh mode is a mode for refreshing all of the memory cells, and the second refresh mode is a mode for refreshing a part of the memory cells. By refreshing only designated areas where data must be retained, power consumption in a refresh operation can be reduced, drastically cutting power consumption in a power-down mode.

    摘要翻译： 刷新存储单元以保留数据的半导体存储器件具有第一刷新模式和第二刷新模式。 第一刷新模式是用于刷新所有存储单元的模式，第二刷新模式是用于刷新存储单元的一部分的模式。 通过仅刷新必须保留数据的指定区域，可以减少刷新操作中的功耗，从而在掉电模式下大幅度地削减功耗。

    Integrated circuit device
    8.
    发明授权
    Integrated circuit device 有权
    集成电路器件

    公开(公告)号：US06194932B1

    公开(公告)日：2001-02-27

    申请号：US09383015

    申请日：1999-08-25

    申请人： Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Nobutaka Taniguchi

    发明人： Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Nobutaka Taniguchi

    IPC分类号： H03L700

    CPC分类号： G11C7/222 ,  G06F1/10 ,  G11C7/22 ,  H03L7/0814

    摘要： The present invention omits a variable delay circuit (10 in FIG. 1) inside a DLL circuit, and instead, creates a timing synchronization circuit, which generates a second reference clock. The timing synchronization circuit shifts the phase of a first reference clock generated by a frequency divider to the timing of a timing signal generated from the other variable delay circuit so that the second reference clock matches to the timing signal. Then, a phase comparator compares the divided first reference clock to a variable clock that delays the second reference clock, and controls the delay time of the variable delay circuit so that both clocks are in phase. As a result, one variable delay circuit can be omitted, and a DLL circuit that uses a divided clock can be configured.

    摘要翻译： 本发明省略了DLL电路内部的可变延迟电路（图1中的10），而是产生产生第二参考时钟的定时同步电路。 定时同步电路将由分频器产生的第一参考时钟的相位移位到从另一个可变延迟电路产生的定时信号的定时，使得第二参考时钟与定​​时信号相匹配。 然后，相位比较器将分频的第一参考时钟与延迟第二参考时钟的可变时钟进行比较，并且控制可变延迟电路的延迟时间，使得两个时钟同相。 结果，可以省略一个可变延迟电路，并且可以配置使用分频时钟的DLL电路。

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06166992A

    公开(公告)日：2000-12-26

    申请号：US517338

    申请日：2000-03-02

    申请人： Yoshihiro Takemae ,  Masao Taguchi ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Takaaki Suzuki ,  Junji Ogawa ,  Atsushi Hatakeyama ,  Hirohiko Mochizuki ,  Hideaki Kawai

    发明人： Yoshihiro Takemae ,  Masao Taguchi ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Takaaki Suzuki ,  Junji Ogawa ,  Atsushi Hatakeyama ,  Hirohiko Mochizuki ,  Hideaki Kawai

    IPC分类号： G06F1/04 ,  G11C7/22 ,  H01L27/02 ,  H03K3/356 ,  H03K5/13 ,  H03K5/1534 ,  H03K5/24 ,  G11C8/00

    CPC分类号： G06F1/04 ,  G11C7/22 ,  G11C7/222 ,  H03K3/356113 ,  H03K3/356156 ,  H03K5/133 ,  H03K5/1534 ,  H03K5/249

    摘要： A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle-time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has a rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

    摘要翻译： 一种半导体器件包括：单触发脉冲发生电路，其在第一时钟信号的上升或下降定时产生具有预定脉冲宽度的单触发脉冲;周期时间测量电路，其测量第一时钟的周期时间 来自单触发脉冲发生电路输出的单触发脉冲的信号;内部时钟发生电路，其基于由周期时间测量电路测量的周期时间和从一个脉冲发生电路输出的单次脉冲产生第二时钟信号 -shot脉冲发生电路。 第二时钟信号具有与第一时钟信号相同的周期时间，并且具有比第一时钟信号高一个特定时间的上升或下降定时，并且通过减去第一时钟信号的周期时间来获得特定时间 时钟信号;以及数据输出电路，其在从第二时钟信号的上升或下降定时之后的预定延迟时间之后输出数据。