公开(公告)号：US07941730B2

公开(公告)日：2011-05-10

申请号：US11443031

申请日：2006-05-31

Applicant: Toshio Ogawa ,  Yoshihiro Takemae ,  Yoshinori Okajima ,  Tetsuhiko Endo ,  Yasuro Matsuzaki

Inventor： Toshio Ogawa ,  Yoshihiro Takemae ,  Yoshinori Okajima ,  Tetsuhiko Endo ,  Yasuro Matsuzaki

IPC: G06F11/10 ,  G06F13/14

CPC classification number: G11C7/10 ,  G06F11/1068 ,  G11C7/1045

Abstract: A semiconductor memory has a field programmable unit in which logic to inter-convert external signals to be input/output to/from a memory system and internal signals to be input/output to/from a memory cell array is programmed. A program for constructing the logic of the field programmable unit is stored in a nonvolatile program memory unit. Through the field programmable unit, a controller can access the memory cell array, even when the interface of the controller accessing the semiconductor memory is different from an interface for accessing the memory cell array. Therefore, one kind of semiconductor memory can be used as plural kinds of semiconductor memories. This eliminates the need to develop plural kinds of semiconductor memories, reducing a development cost.

Abstract translation: 半导体存储器具有现场可编程单元，其中将外部信号互相转换为存储器系统的输入/输出的逻辑和要从存储器单元阵列输入/输出的内部信号的逻辑被编程。 用于构建现场可编程单元的逻辑的程序存储在非易失性程序存储单元中。 通过现场可编程单元，即使当访问半导体存储器的控制器的接口与用于访问存储单元阵列的接口不同时，控制器也可以访问存储单元阵列。 因此，可以使用一种半导体存储器作为多种半导体存储器。 这消除了开发多种半导体存储器的需要，降低了开发成本。

公开(公告)号：US07533196B2

公开(公告)日：2009-05-12

申请号：US11589840

申请日：2006-10-31

Applicant: Masayoshi Tojima ,  Hiroshi Miyajima ,  Yoshinori Okajima

Inventor： Masayoshi Tojima ,  Hiroshi Miyajima ,  Yoshinori Okajima

IPC: G06F13/28

CPC classification number: G06F12/0692 ,  G06F15/7857

Abstract: A semiconductor integrated circuit device includes a plurality of internal memories, a main processor, which constitutes a first processing unit having a codec function, and a video interface and graphics processor, which constitute a second processing unit for video display processing. The semiconductor integrated circuit device operates while being connected to a CPU, which is an external processing unit, and an external memory. The semiconductor integrated circuit device is provided with a memory configuration controller for controlling the memory allocation to the first, the second, and the external processing unit in accordance with an application.

Abstract translation: 半导体集成电路装置包括多个内部存储器，构成具有编解码功能的第一处理单元的主处理器，以及构成用于视频显示处理的第二处理单元的视频接口和图形处理器。 半导体集成电路器件在连接到作为外部处理单元的CPU和外部存储器时工作。 半导体集成电路装置具有存储器配置控制器，用于根据应用控制对第一，第二和外部处理单元的存储器分配。

公开(公告)号：US07428182B1

公开(公告)日：2008-09-23

申请号：US09372166

申请日：1999-08-11

Applicant: Yoshinori Okajima

Inventor： Yoshinori Okajima

IPC: G11C8/00

CPC classification number: H04L12/42

Abstract: An electronic circuit system has at least three macro circuits and a plurality of signal lines for connecting the macro circuits to one another into a loop. Each of the macro circuits includes a logic circuit and a memory circuit and has a plurality of input terminals and a plurality of output terminals. Signals are transmitted through the loop in a single specified direction in synchronization with a clock signal. Each of the macro circuits receives the signals at the input terminals thereof, accepts the signals if the signals are destined for the macro circuit, and transfers the signals to the output terminals thereof if the signals are not destined for the macro circuit. Even if the macro circuits simultaneously transmit signals, the electronic circuit system transmits the signals in the specified direction through the loop in synchronization with the clock signal up to destination macro circuits.

Abstract translation: 电子电路系统具有至少三个宏电路和用于将宏电路彼此连接成环路的多条信号线。 宏电路中的每一个包括逻辑电路和存储电路，并且具有多个输入端子和多个输出端子。 信号与时钟信号同步地在单个指定方向上通过环路传输。 每个宏电路在其输入端接收信号，如果信号指向宏电路，则接收信号，并且如果信号不是用于宏电路，则将信号传送到其输出端。 即使宏电路同时发送信号，电子电路系统也可以与到目标宏电路的时钟信号同步地通过环路在指定方向上发送信号。

公开(公告)号：US07417884B2

公开(公告)日：2008-08-26

申请号：US11443030

申请日：2006-05-31

Applicant: Toshio Ogawa ,  Yoshihiro Takemae ,  Yoshinori Okajima ,  Tetsuhiko Endo ,  Yasuro Matsuzaki

Inventor： Toshio Ogawa ,  Yoshihiro Takemae ,  Yoshinori Okajima ,  Tetsuhiko Endo ,  Yasuro Matsuzaki

IPC: G11C5/06 ,  H04B10/00

CPC classification number: G06F13/4243 ,  G11C5/066 ,  G11C7/1006

Abstract: A memory controller multiplexes access signals each consisting of a plurality of bits as optical signals and outputs the multiplexed optical signals. At this time, the optical signals whose wavelengths differ depending on memory devices are generated. A memory interface unit demultiplexes the multiplexed optical signals into the original optical signals and converts the demultiplexed optical signals into electrical signals. The memory interface unit determines to which of the memory devices the electrical signals resulting from the conversion should be outputted, according to the wavelengths of the demultiplexed optical signals. This frees the memory controller from a need for transmitting to the memory interface unit a signal for identifying the memory device. The memory interface unit need not include a decoding circuit for identifying the memory device.

Abstract translation: 存储器控制器将每个由多个位组成的访问信号复用为光信号并输出​​复用的光信号。 此时，产生根据存储器件波长不同的光信号。 存储器接口单元将复用的光信号解复用为原始光信号，并将解复用的光信号转换为电信号。 存储器接口单元根据解复用的光信号的波长来确定应该向哪个存储器件输出由转换产生的电信号。 这使得存储器控制器不需要向存储器接口单元发送用于识别存储器件的信号。 存储器接口单元不需要包括用于识别存储器件的解码电路。

公开(公告)号：US20070192527A1

公开(公告)日：2007-08-16

申请号：US11443031

申请日：2006-05-31

Applicant: Toshio Ogawa ,  Yoshihiro Takemae ,  Yoshinori Okajima ,  Tetsuhiko Endo ,  Yasuro Matsuzaki

Inventor： Toshio Ogawa ,  Yoshihiro Takemae ,  Yoshinori Okajima ,  Tetsuhiko Endo ,  Yasuro Matsuzaki

IPC: G06F12/00

CPC classification number: G11C7/10 ,  G06F11/1068 ,  G11C7/1045

Abstract: A semiconductor memory has a field programmable unit in which logic to inter-convert external signals to be input/output to/from a memory system and internal signals to be input/output to/from a memory cell array is programmed. A program for constructing the logic of the field programmable unit is stored in a nonvolatile program memory unit. Through the field programmable unit, a controller can access the memory cell array, even when the interface of the controller accessing the semiconductor memory is different from an interface for accessing the memory cell array. Therefore, one kind of semiconductor memory can be used as plural kinds of semiconductor memories. This eliminates the need to develop plural kinds of semiconductor memories, reducing a development cost.

Abstract translation: 半导体存储器具有现场可编程单元，其中将外部信号互相转换为存储器系统的输入/输出的逻辑和要从存储器单元阵列输入/输出的内部信号的逻辑被编程。 用于构建现场可编程单元的逻辑的程序存储在非易失性程序存储单元中。 通过现场可编程单元，即使当访问半导体存储器的控制器的接口与用于访问存储单元阵列的接口不同时，控制器也可以访问存储单元阵列。 因此，可以使用一种半导体存储器作为多种半导体存储器。 这消除了开发多种半导体存储器的需要，降低了开发成本。

公开(公告)号：US20070188210A1

公开(公告)日：2007-08-16

申请号：US11723602

申请日：2007-03-21

Applicant: Yoshinori Okajima

Inventor： Yoshinori Okajima

IPC: H03H11/26

CPC classification number: H03H11/265 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00039 ,  H03L7/0812

Abstract: A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.

Abstract translation: 受控延迟电路具有第一栅极链和第二栅极链。 第一栅极链用于测量第一控制信号的转换点和第二控制信号的转换点之间的时间差。 接收在第一门链中产生并表示时间差的第三信号的第二门链用于根据时间差从输入到输出提供适当的延迟时间。 受控延迟电路能够根据控制信号的周期适当地控制控制信号的定时。

公开(公告)号：US06384671B1

公开(公告)日：2002-05-07

申请号：US09541699

申请日：2000-04-03

Applicant: Masao Taguchi ,  Satoshi Eto ,  Yoshinori Okajima

Inventor： Masao Taguchi ,  Satoshi Eto ,  Yoshinori Okajima

IPC: G05F110

CPC classification number: H04L25/0278 ,  H03K17/16 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/0298

Abstract: An electronic circuit apparatus having a bus, a plurality of stubs branched from the bus, and a plurality of semiconductor devices having signal input/output terminals connected to the corresponding stubs. The electronic circuit apparatus includes at least one impedance circuit arranged between the bus and at least one of the stubs, and each impedance circuit has a high-pass filter characteristic. Therefore, ringing is suppressed, attenuation in the high-frequency components of a transmission signal is prevented, the definition of the signal is maintained, and transmission frequency and speed are both improved.

Abstract translation: 具有总线，从总线分支的多个短截线的电子电路装置以及具有连接到对应短线的信号输入/输出端子的多个半导体器件。 电子电路装置包括布置在总线和至少一个短截线之间的至少一个阻抗电路，并且每个阻抗电路具有高通滤波器特性。 因此，抑制振铃，防止传输信号的高频分量的衰减，维持信号的定义，并且提高传输频率和速度。

公开(公告)号：US6114890A

公开(公告)日：2000-09-05

申请号：US967658

申请日：1997-11-10

Applicant: Yoshinori Okajima ,  Tsuyoshi Higuchi

Inventor： Yoshinori Okajima ,  Tsuyoshi Higuchi

IPC: H03L7/081 ,  H03L7/087 ,  H03K5/12

CPC classification number: H03L7/0805 ,  H03L7/0814 ,  H03L7/087

Abstract: A circuit includes a first phase-adjustment circuit adjusting phases of rising edges and falling edges of an original signal, and a phase-delay circuit receiving a phase-adjusted signal from said first phase-adjustment circuit and generating a delay signal by delaying said phase-adjusted signal by a predetermined phase amount. The circuit further includes a phase-comparison circuit comparing phases of edges between said phase-adjusted signal and said delay signal so as to control said first phase-adjustment circuit such that said phases of edges satisfy a predetermined phase relation.

Abstract translation: 电路包括调整原始信号的上升沿和下降沿的相位的第一相位调整电路，以及从所述第一相位调整电路接收相位调整信号的相位延迟电路，并通过延迟所述相位产生延迟信号 - 调整信号预定相位量。 电路还包括相位比较电路，比较所述相位调整信号和所述延迟信号之间的边沿的相位，以便控制所述第一相位调整电路，使得所述边缘相位满足预定的相位关系。

公开(公告)号：US4744060A

公开(公告)日：1988-05-10

申请号：US788567

申请日：1985-10-17

Applicant: Yoshinori Okajima

Inventor： Yoshinori Okajima

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/84

Abstract: A semiconductor memory device of a bipolar-transistor type including a memory cell array, a redundancy array, a defective address memory circuit for storing a defective address and a comparing circuit for comparing an input address with the defective address. The defective address memory circuit includes a plurality of information memory circuits. The information memory circuits include a plurality of diode stages for determining their output amplitudes. When an input address coincides with the defective address stored in the address memory circuit, the redundancy array is selected instead of the memory cell array.

Abstract translation: 一种双极型晶体管型半导体存储器件，包括存储单元阵列，冗余阵列，用于存储缺陷地址的缺陷地址存储电路和用于比较输入地址与缺陷地址的比较电路。 缺陷地址存储电路包括多个信息存储电路。 信息存储电路包括用于确定其输出振幅的多个二极管级。 当输入地址与存储在地址存储器电路中的缺陷地址一致时，选择冗余阵列而不是存储单元阵列。

公开(公告)号：US4675555A

公开(公告)日：1987-06-23

申请号：US813941

申请日：1985-12-27

Applicant: Yoshinori Okajima ,  Masaki Ohiwa

Inventor： Yoshinori Okajima ,  Masaki Ohiwa

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/118 ,  H03K19/018 ,  H03K19/086 ,  H03K19/013

CPC classification number: H03K19/086 ,  H01L27/11801 ,  H03K19/01825

Abstract: In a semiconductor device including a plurality of input signal pads (P.sub.0, . . . , P.sub.7); a plurality of emitter followers (Q.sub.01, . . . , Q.sub.71) are connected to the input signal pads (P.sub.0, . . . , P.sub.7); a plurality of input signal buffers (BUF.sub.0, . . . , BUF.sub.7) are connected to the emitter followers (Q.sub.01, . . . , Q.sub.71); and a plurality of constant current sources (I.sub.01, . . . , I.sub.71) are connected to the emitter followers (Q.sub.01, . . . , Q.sub.71). The emitter followers (Q.sub.01, . . . , Q.sub.71) are in proximity to the input signal pads (P.sub.0, . . . , P.sub.7), and the constant current sources (I.sub.0, . . . , I.sub.7) are in proximity to the emitter followers (Q.sub.01, . . . , Q.sub.71) . The current values of the constant current sources (I.sub.01, . . . , I.sub.71 ) are determined in accordance with the length of the corresponding connections between the emitter followers (Q.sub.01, . . . , Q.sub.71) and the input signal buffers (BUF.sub.0, . . . , BUF.sub.7).

Abstract translation: 在包括多个输入信号焊盘（P0，...，P7）的半导体器件中; 多个发射极跟随器（Q01，...，Q71）连接到输入信号焊盘（P0，...，P7）; 多个输入信号缓冲器（BUF0，...，BUF7）连接到发射极跟随器（Q01，...，Q71）; 和多个恒定电流源（I01，...，I71）连接到发射极跟随器（Q01，...，Q71）。 发射极跟随器（Q01，...，Q71）接近输入信号焊盘（P0，...，P7），恒流源（I0，...，I7）接近发射极 追随者（Q01，... Q71）。 根据发射极跟随器（Q01，...，Q71）和输入信号缓冲器（BUF0，...）之间的对应连接的长度来确定恒定电流源（I01，...，I71）的当前值。 ...，BUF7）。