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    Two-part hair dye
    3.
    发明授权
    Two-part hair dye 有权
    两部分染发剂

    公开(公告)号：US08460398B2

    公开(公告)日：2013-06-11

    申请号：US13509735

    申请日：2010-11-30

    Applicant: Yuki Naoi ,  Yoshinori Saito ,  Toshio Ogawa

    Inventor： Yuki Naoi ,  Yoshinori Saito ,  Toshio Ogawa

    IPC: A61Q5/10

    CPC classification number: A61Q5/10 ,  A61K8/046 ,  A61K8/342 ,  A61K8/86 ,  A61K2800/88

    Abstract: A two-part hair dye including a first part containing an alkali agent, a second part containing hydrogen peroxide, and a non-aerosol foamer container; wherein a liquid mixture contains Components (A) and (B) specified below, wherein the content of hydrogen peroxide in the liquid mixture is 3.60 mass % or higher, and the viscosity of the liquid mixture is 1 to 300 mPa·s. A method for dying hair, wherein a foam of the liquid mixture of the first part and the second part of the two-part hair dye is applied to hair, left to stand for 3 to 60 minutes, and then washed out. Component (A): oxidation dye; Component (B): 0.50 to 3.0 mass %, of polypropylene glycol having a weight-average molecular weight of 200 to 800.

    Abstract translation: 包括含有碱剂的第一部分，含有过氧化氢的第二部分和非气溶胶发泡剂容器的两部分染发剂; 其中，液体混合物含有下述的成分（A）和（B），其中，液体混合物中过氧化氢的含量为3.60质量％以上，液体混合物的粘度为1〜300mPa·s。 一种染色头发的方法，其中将两部分染发剂的第一部分和第二部分的液体混合物的泡沫施加到头发上，静置3至60分钟，然后洗掉。 组分（A）：氧化染料; 成分（B）：0.50〜3.0质量％的重均分子量为200〜800的聚丙二醇。

    Memory system
    6.
    发明授权
    Memory system 有权
    内存系统

    公开(公告)号：US07941730B2

    公开(公告)日：2011-05-10

    申请号：US11443031

    申请日：2006-05-31

    Applicant: Toshio Ogawa ,  Yoshihiro Takemae ,  Yoshinori Okajima ,  Tetsuhiko Endo ,  Yasuro Matsuzaki

    Inventor： Toshio Ogawa ,  Yoshihiro Takemae ,  Yoshinori Okajima ,  Tetsuhiko Endo ,  Yasuro Matsuzaki

    IPC: G06F11/10 ,  G06F13/14

    CPC classification number: G11C7/10 ,  G06F11/1068 ,  G11C7/1045

    Abstract: A semiconductor memory has a field programmable unit in which logic to inter-convert external signals to be input/output to/from a memory system and internal signals to be input/output to/from a memory cell array is programmed. A program for constructing the logic of the field programmable unit is stored in a nonvolatile program memory unit. Through the field programmable unit, a controller can access the memory cell array, even when the interface of the controller accessing the semiconductor memory is different from an interface for accessing the memory cell array. Therefore, one kind of semiconductor memory can be used as plural kinds of semiconductor memories. This eliminates the need to develop plural kinds of semiconductor memories, reducing a development cost.

    Abstract translation: 半导体存储器具有现场可编程单元，其中将外部信号互相转换为存储器系统的输入/输出的逻辑和要从存储器单元阵列输入/输出的内部信号的逻辑被编程。 用于构建现场可编程单元的逻辑的程序存储在非易失性程序存储单元中。 通过现场可编程单元，即使当访问半导体存储器的控制器的接口与用于访问存储单元阵列的接口不同时，控制器也可以访问存储单元阵列。 因此，可以使用一种半导体存储器作为多种半导体存储器。 这消除了开发多种半导体存储器的需要，降低了开发成本。

    Designing and operating of semiconductor integrated circuit by taking into account process variation
    7.
    发明授权
    Designing and operating of semiconductor integrated circuit by taking into account process variation 失效
    考虑到工艺变化，设计和运行半导体集成电路

    公开(公告)号：US07661079B2

    公开(公告)日：2010-02-09

    申请号：US11525895

    申请日：2006-09-25

    Applicant: Toshio Ogawa

    Inventor： Toshio Ogawa

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A method of designing a semiconductor integrated circuit includes defining a tolerable range in which an operating temperature and an operating power supply voltage of a semiconductor integrated circuit are allowed to vary, computing a target temperature and a target power supply voltage that cancel variation in circuit characteristics caused by process variation of the semiconductor integrated circuit, separately for each circuit characteristic responsive to the process variation, and designing the semiconductor integrated circuit such that the semiconductor integrated circuit properly operates with any temperature and power supply voltage within the tolerable range based on an assumption that the semiconductor integrated circuit is to operate within the tolerable range centered substantially at the target temperature and target power supply voltage.

    Abstract translation: 一种设计半导体集成电路的方法包括限定可容许的范围，其中允许半导体集成电路的工作温度和工作电源电压发生变化，计算目标温度和抵消电路特性变化的目标电源电压 由半导体集成电路的工艺变化引起的，分别针对响应于工艺变化的每个电路特性，以及设计半导体集成电路，使得半导体集成电路基于假定在可容忍范围内的任何温度和电源电压适当地工作 半导体集成电路将在基本上以目标温度和目标电源电压为中心的容许范围内工作。

    Memory system
    8.
    发明授权
    Memory system 有权
    内存系统

    公开(公告)号：US07417884B2

    公开(公告)日：2008-08-26

    申请号：US11443030

    申请日：2006-05-31

    Applicant: Toshio Ogawa ,  Yoshihiro Takemae ,  Yoshinori Okajima ,  Tetsuhiko Endo ,  Yasuro Matsuzaki

    Inventor： Toshio Ogawa ,  Yoshihiro Takemae ,  Yoshinori Okajima ,  Tetsuhiko Endo ,  Yasuro Matsuzaki

    IPC: G11C5/06 ,  H04B10/00

    CPC classification number: G06F13/4243 ,  G11C5/066 ,  G11C7/1006

    Abstract: A memory controller multiplexes access signals each consisting of a plurality of bits as optical signals and outputs the multiplexed optical signals. At this time, the optical signals whose wavelengths differ depending on memory devices are generated. A memory interface unit demultiplexes the multiplexed optical signals into the original optical signals and converts the demultiplexed optical signals into electrical signals. The memory interface unit determines to which of the memory devices the electrical signals resulting from the conversion should be outputted, according to the wavelengths of the demultiplexed optical signals. This frees the memory controller from a need for transmitting to the memory interface unit a signal for identifying the memory device. The memory interface unit need not include a decoding circuit for identifying the memory device.

    Abstract translation: 存储器控制器将每个由多个位组成的访问信号复用为光信号并输出​​复用的光信号。 此时，产生根据存储器件波长不同的光信号。 存储器接口单元将复用的光信号解复用为原始光信号，并将解复用的光信号转换为电信号。 存储器接口单元根据解复用的光信号的波长来确定应该向哪个存储器件输出由转换产生的电信号。 这使得存储器控制器不需要向存储器接口单元发送用于识别存储器件的信号。 存储器接口单元不需要包括用于识别存储器件的解码电路。

    Memory system
    9.
    发明申请
    Memory system 有权
    内存系统

    公开(公告)号：US20070192527A1

    公开(公告)日：2007-08-16

    申请号：US11443031

    申请日：2006-05-31

    Applicant: Toshio Ogawa ,  Yoshihiro Takemae ,  Yoshinori Okajima ,  Tetsuhiko Endo ,  Yasuro Matsuzaki

    Inventor： Toshio Ogawa ,  Yoshihiro Takemae ,  Yoshinori Okajima ,  Tetsuhiko Endo ,  Yasuro Matsuzaki

    IPC: G06F12/00

    CPC classification number: G11C7/10 ,  G06F11/1068 ,  G11C7/1045

    Abstract: A semiconductor memory has a field programmable unit in which logic to inter-convert external signals to be input/output to/from a memory system and internal signals to be input/output to/from a memory cell array is programmed. A program for constructing the logic of the field programmable unit is stored in a nonvolatile program memory unit. Through the field programmable unit, a controller can access the memory cell array, even when the interface of the controller accessing the semiconductor memory is different from an interface for accessing the memory cell array. Therefore, one kind of semiconductor memory can be used as plural kinds of semiconductor memories. This eliminates the need to develop plural kinds of semiconductor memories, reducing a development cost.

    Abstract translation: 半导体存储器具有现场可编程单元，其中将外部信号互相转换为存储器系统的输入/输出的逻辑和要从存储器单元阵列输入/输出的内部信号的逻辑被编程。 用于构建现场可编程单元的逻辑的程序存储在非易失性程序存储单元中。 通过现场可编程单元，即使当访问半导体存储器的控制器的接口与用于访问存储单元阵列的接口不同时，控制器也可以访问存储单元阵列。 因此，可以使用一种半导体存储器作为多种半导体存储器。 这消除了开发多种半导体存储器的需要，降低了开发成本。

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