发明授权
US6078514A Semiconductor device and semiconductor system for high-speed data
transfer
失效
半导体器件和半导体系统，用于高速数据传输
- 专利标题： Semiconductor device and semiconductor system for high-speed data transfer
- 专利标题（中）： 半导体器件和半导体系统，用于高速数据传输
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申请号： US61023申请日： 1998-04-16
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公开(公告)号： US6078514A公开(公告)日： 2000-06-20
- 发明人: Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Takaaki Suzuki , Hiroyoshi Tomita , Toshiya Uchida , Yasuharu Sato , Atsushi Hatakeyama , Masato Matsumiya , Yasurou Matsuzaki
- 申请人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Takaaki Suzuki , Hiroyoshi Tomita , Toshiya Uchida , Yasuharu Sato , Atsushi Hatakeyama , Masato Matsumiya , Yasurou Matsuzaki
- 申请人地址： JPX Kanagawa
- 专利权人： Fujitsu Limited
- 当前专利权人： Fujitsu Limited
- 当前专利权人地址： JPX Kanagawa
- 优先权： JPX9-244285 19970909
- 主分类号： G11C11/41
- IPC分类号： G11C11/41 ; G11C7/10 ; G11C7/22 ; G11C11/401 ; H01L21/60 ; H01L25/00 ; H01L27/10 ; H01L25/04 ; H01L23/36
摘要：
A semiconductor system includes at least one logic chip and at least one memory chip arranged such that one side of the at least one memory chip faces one side of the at least one logic chip. The semiconductor system further includes first input/output nodes, provided for the at least one logic chip, for data transfer with an adjacent memory chip, second input/output nodes, provided for the at least one memory chip, for data transfer with an adjacent logic chip, and a package housing the at least one logic chip and the at least one memory chip, wherein the first input/output nodes are arranged along the one side of the at least one logic chip, and the second input/output nodes are arranged along the one side of the at least one memory chip.
公开/授权文献
- USD401341S Psychotherapeutic flaccid penile prosthetic 公开/授权日：1998-11-17
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