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    METHOD FOR ENHANCING FORM RETENTION PROPERTY OF BEVERAGE
    1.
    发明申请
    METHOD FOR ENHANCING FORM RETENTION PROPERTY OF BEVERAGE 审中-公开
    提高饮料保鲜性能的方法

    公开(公告)号：US20110020512A1

    公开(公告)日：2011-01-27

    申请号：US12508110

    申请日：2009-07-23

    Applicant: Kenji MASUTAKE ,  Yasuharu SATO ,  Kazuhiko NISHIMURA

    Inventor： Kenji MASUTAKE ,  Yasuharu SATO ,  Kazuhiko NISHIMURA

    IPC: A23C3/08 ,  A23C9/152 ,  A23L2/02

    CPC classification number: A23F5/40 ,  A23C9/1524 ,  A23C9/1542 ,  A23C9/1544 ,  A23C2210/30 ,  A23L2/02 ,  A23L2/52 ,  A23L2/54 ,  A23P30/40

    Abstract: The present invention provides a method for enhancing a foam retention property of a beverage, and in addition a method for stably retaining foam in a beverage, the foam obtained by shaking the beverage, by enhancing the foam retention property. The present invention is implemented by preparing a beverage by using a fermentation-derived cellulose as a raw material thereof, more preferably by preparing a beverage by using a fermentation-derived cellulose in a state of complex with a high molecular substance.

    Abstract translation: 本发明提供了一种提高饮料泡沫保持性的方法，另外还提供了一种在饮料中稳定地保持泡沫的方法，通过提高泡沫保持性来摇动饮料而获得的泡沫。 本发明通过使用发酵衍生的纤维素作为原料制备饮料来实现，更优选通过使用与高分子物质复合的发酵衍生的纤维素制备饮料来实现。

    Semiconductor memory improved for testing
    3.
    发明授权
    Semiconductor memory improved for testing 有权
    半导体存储器改进了测试

    公开(公告)号：US06721910B2

    公开(公告)日：2004-04-13

    申请号：US09400831

    申请日：1999-09-21

    Applicant: Kazuhiro Ninomiya ,  Shinya Fujioka ,  Yasuharu Sato

    Inventor： Kazuhiro Ninomiya ,  Shinya Fujioka ,  Yasuharu Sato

    IPC: G11C2900

    CPC classification number: G11C5/063 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008 ,  G11C2207/2254

    Abstract: A synchronous DRAM (SDRAM) or a fast cycle RAM (FCRAM) includes capacitors connected by switches to a signal wire. The switches are controlled to connect and disconnect the capacitors to the signal wire. In a test mode, the transmission time of a control signal is tested by connecting various combinations of the capacitors to the signal wire, and then measuring the signal timing. The signal timing of the memory device can be controlled by selecting which and how many of the capacitors are connected to the signal wire.

    Abstract translation: 同步DRAM（SDRAM）或快速周期RAM（FCRAM）包括通过开关连接到信号线的电容器。 控制开关将电容器连接到信号线。 在测试模式下，通过将各种电容器的组合连接到信号线，然后测量信号时序来测试控制信号的传输时间。 可以通过选择哪个和多少电容器连接到信号线来控制存储器件的信号定时。

    Semiconductor integrated circuit device capable of outputting leading data of a series of multiple burst-readout data without delay
    4.
    发明授权
    Semiconductor integrated circuit device capable of outputting leading data of a series of multiple burst-readout data without delay 有权
    半导体集成电路装置能够不延迟地输出一连串的多脉冲串读出数据的引导数据

    公开(公告)号：US06715115B1

    公开(公告)日：2004-03-30

    申请号：US09615953

    申请日：2000-07-13

    Applicant: Tadao Aikawa ,  Yasuharu Sato

    Inventor： Tadao Aikawa ,  Yasuharu Sato

    IPC: G11C2900

    CPC classification number: G11C29/1201 ,  G11C7/1027 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C29/12 ,  G11C2207/105 ,  G11C2207/107

    Abstract: A semiconductor device including a parallel to serial conversion circuit that receives first through nth data (where n is an integer greater than or equal to 2), together with (n+1)th data, in parallel to each other, and that outputs the first through nth data in series in this order via first through nth paths in a first operating mode, while it outputs the (n+1)th data via one of the second through nth paths in a second operation mode. An output control circuit is connected to the parallel to serial conversion circuit via the first through nth paths, the output control circuit successively outputting the first through nth data in the first operating mode, and outputting only the (n+1)th data supplied from the parallel to serial conversion circuit in the second operating mode.

    Abstract translation: 包括并行到串行转换电路的半导体器件与第（n + 1）个数据并行地接收第一至第n个数据（其中n是大于或等于2的整数） ，并且在第一操作模式中，通过第一至第n路径以该顺序依次输出第一至第n个数据，同时通过第二至第n个数据中的一个输出第（n + 1）个数据， 第二操作模式中的路径。 输出控制电路经由第一至第n路连接到并行到串行转换电路，输出控制电路在第一操作模式中连续地输出第一至第n个数据，并且仅输出第（n + 1）个 在第二操作模式中从并行到串行转换电路提供的数据。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US06459641B2

    公开(公告)日：2002-10-01

    申请号：US09834945

    申请日：2001-04-16

    Applicant: Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

    Inventor： Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

    IPC: G11C700

    CPC classification number: G11C7/06 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005 ,  G11C2207/065

    Abstract: The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.

    Abstract translation: 本发明的目的在于提供一种在访问不同行地址时执行行地址管线操作以实现高速访问的半导体存储器件。 根据本发明的半导体存储器件包括多个读出放大器，当经由位线从存储器单元接收数据时存储数据，该存储器单元对应于所选择的字线，列解码器从多个位读取多个位的并行数据 选择的读出放大器，通过响应于列地址同时选择多个列门，将并行数据转换为串行数据的数据转换单元，以及产生内部预充电信号的预充电信号产生单元， 生成用于选择所选字线的行访问信号以便复位位线和所述多个感测放大器之后的时间段。

    Semiconductor integrated circuit and method for controlling the same
    8.
    发明授权
    Semiconductor integrated circuit and method for controlling the same 有权
    半导体集成电路及其控制方法

    公开(公告)号：US06353561B1

    公开(公告)日：2002-03-05

    申请号：US09397845

    申请日：1999-09-17

    Applicant: Akihiro Funyu ,  Shinya Fujioka ,  Yasuharu Sato ,  Toshiya Uchida

    Inventor： Akihiro Funyu ,  Shinya Fujioka ,  Yasuharu Sato ,  Toshiya Uchida

    IPC: G11C700

    CPC classification number: G11C7/109 ,  G11C7/1006 ,  G11C7/1072 ,  G11C7/1078 ,  G11C11/4093

    Abstract: A semiconductor memory device, such as a synchronous DRAM, receives external commands and an external clock signal via input buffers. The device generates internal clock signals having a slower frequency than the external clock signal and uses the internal clock signals to acquire the external command. This allows more than one external command to be acquired for each cycle of the external clock. The acquired external commands are provided to command decoders for decoding. A mask circuit is connected to the decoder circuits and inhibits the decoding circuits, except for a first one of the decoding circuits, from decoding the external commands for a predetermined time period, when the first decoder circuit is decoding the external commands.

    Abstract translation: 诸如同步DRAM的半导体存储器件经由输入缓冲器接收外部命令和外部时钟信号。 该器件产生的频率低于外部时钟信号的内部时钟信号，并使用内部时钟信号来获取外部命令。 这允许在外部时钟的每个周期获取多于一个外部命令。 获取的外部命令被提供给命令解码器进行解码。 当第一解码器电路解码外部命令时，掩码电路连接到解码器电路，并且禁止解码电路以外的第一解码电路在预定时间段内解码外部命令。

    Semiconductor integrated circuit
    10.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US06192004B1

    公开(公告)日：2001-02-20

    申请号：US09559743

    申请日：2000-04-27

    Applicant: Tadao Aikawa ,  Yasuharu Sato

    Inventor： Tadao Aikawa ,  Yasuharu Sato

    IPC: G11C800

    CPC classification number: G11C7/222 ,  G11C7/1072 ,  G11C7/22 ,  H03K5/1534

    Abstract: A clock pulse generator generates a plurality of clock pulses which has different phases during one cycle of a reference clock signal supplied from the exterior. A timing setting circuit sets a latency, which is a number of clock cycles from a start of a read operation to an output of read data, at a number which is divisible by one n-th (n=2, 3, 4 . . . ) of a cycle of the reference clock signal and outputs latency information according to the set latency. An output controlling pulse switching circuit respectively outputs each of the clock pulses as a predetermined output controlling pulse in accordance with the latency information. In other words, a plurality of the output controlling pulses are switched according to the latency information. In synchronization with each of the output controlling pulses, a data outputting circuit sequentially and respectively converts parallel data, read from a plurality of memory cells stored with data, into serial data and respectively outputs the converted serial data during the predetermined period according to the latency. No matter what timing of the reference clock signal the latency might be set at, therefore, the serial data can be reliably outputted without switching the parallel data. The data are outputted at high speed because the parallel data need not be switched.

    Abstract translation: 时钟脉冲发生器在从外部提供的参考时钟信号的一个周期期间产生具有不同相位的多个时钟脉冲。 定时设定电路将从读取操作开始到读取数据的输出的时钟周期数设定为可以被第n个（n = 2,3,4，...）整除的数字。 ），并且根据设定的等待时间输出等待时间信息。 输出控制脉冲切换电路根据等待时间信息分别输出每个时钟脉冲作为预定的输出控制脉冲。 换句话说，根据等待时间信息来切换多个输出控制脉冲。 与每个输出控制脉冲同步，数据输出电路依次分别将从数据存储的多个存储单元中读取的并行数据转换为串行数据，并根据延迟分别在预定时段内输出转换后的串行数据 。 无论参考时钟信号的时序如何，延迟可能被设置，因此，可以可靠地输出串行数据，而无需切换并行数据。 由于不需要切换并行数据，因此高速输出数据。

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