公开(公告)号：US5537354A

公开(公告)日：1996-07-16

申请号：US357307

申请日：1994-12-14

Applicant: Hirohiko Mochizuki ,  Yoshihiro Takemae ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Hiroyoshi Tomita

Inventor： Hirohiko Mochizuki ,  Yoshihiro Takemae ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Hiroyoshi Tomita

IPC: G11C11/401 ,  F02B75/02 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C13/00

CPC classification number: G11C7/1072 ,  F02B2075/025

Abstract: A method of making an SDRAM (synchronous dynamic random access memory) into either a low-speed type or a high-speed type includes the steps of determining an electrical connection of a predetermined electrode of the SDRAM, and providing the predetermined electrode with a voltage level defined by the electrical connection, the voltage level determining whether the SDRAM is made into the low-speed type or the high speed type, wherein the low-speed type can carry out consecutive writing operations at a low clock rate for two addresses having the same row address, and the high-speed type can carry out simultaneous writing operations at a high clock rate for two addresses having the same row address and consecutive column addresses.

Abstract translation: 将SDRAM（同步动态随机存取存储器）制成低速型或高速型的方法包括以下步骤：确定SDRAM的预定电极的电连接，并为预定电极提供电压 由电气连接限定的电平，电压电平确定SDRAM是低速型还是高速型，其中低速类型可以以低时钟速率对具有 相同的行地址，并且高速类型可以以具有相同行地址和连续列地址的两个地址以高时钟速率执行同时写入操作。

公开(公告)号：US4932000A

公开(公告)日：1990-06-05

申请号：US355630

申请日：1989-05-23

Applicant: Yukinori Kodama ,  Takaaki Furuyama

Inventor： Yukinori Kodama ,  Takaaki Furuyama

IPC: G11C11/407 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  H01L21/8242 ,  H01L27/108

CPC classification number: G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of word lines; a row pre-decoding unit responsive to a row address signal, outputting a plurality of row pre-decode signals with units of a group having signals of a number corresponding to a combination of each logic level of a predetermined plurality of bits of the row address signal; a row pre-decode wiring for transmitting the plurality of row pre-decode signals; a row main decoder responsive to one signal in each group of the plurality of row pre-decode signals, carrying out a main decoding for selecting one of the plurality of word lines; a pseudo row decoder having substantially same electrical characteristics as the row main decoder, carrying out a simulation of the main decoding in response to the plurality of row pre-decode signals output on row pre-decode wiring; and a word line driver for driving a word line selected by the row main decoder to a predetermined level. An operation of the word line driver is started in response to an activation of the pseudo row decoder, thereby excluding a possibility of an erroneous selection of a word line and preventing an unnecessary prolongation of an access time.

公开(公告)号：US4821232A

公开(公告)日：1989-04-11

申请号：US97556

申请日：1987-09-16

Applicant: Masao Nakano ,  Tsuyoshi Ohira ,  Hirohiko Mochizuki ,  Yukinori Kodama ,  Hidenori Nomura

Inventor： Masao Nakano ,  Tsuyoshi Ohira ,  Hirohiko Mochizuki ,  Yukinori Kodama ,  Hidenori Nomura

IPC: G11C11/409 ,  G11C7/10 ,  G11C7/20 ,  G11C13/00 ,  G11C11/40

CPC classification number: G11C7/20 ,  G11C7/1048

Abstract: A semiconductor memory device comprises a memory cell array comprising a plurality of memory cells arranged in a matrix arrangement, a sense amplifier, operatively connected to the memory cell array, amplifying a signal read out from one of the memory cells and having a pair of output terminals for outputting a complementary signal, a pair of data buses for transferring the complementary signal, a transfer gate for connecting the pair of output terminals to the pair of data buses responsive to a read operation, a data output buffer connected to the pair of data buses for outputting an output signal, and a reset circuit for resetting the pair of data buses to a predetermined voltage before each read operation responsive to a reset clock signal. The reset circuit comprises a first circuit connected to the pair of data buses for connecting the pair of data buses to a common node responsive to the reset clock signal, and a second circuit connected between the common node and a ground voltage for shifting a potential at the common node to a voltage which is the predetermined voltage greater than the ground voltage.

Abstract translation: 半导体存储器件包括存储单元阵列，该存储单元阵列包括以矩阵布置的多个存储单元，读出放大器，可操作地连接到存储单元阵列，放大从一个存储单元读出的信号，并具有一对输出 用于输出互补信号的端子，用于传送互补信号的一对数据总线，用于响应于读取操作将一对输出端连接到该对数据总线的传输门，连接到该对数据的数据输出缓冲器 用于输出输出信号的总线;以及复位电路，用于响应于复位时钟信号在每次读取操作之前将该对数据总线复位到预定电压。 复位电路包括连接到该对数据总线的第一电路，用于响应于复位时钟信号将一对数据总线连接到公共节点，以及连接在公共节点和接地电压之间的第二电路， 该公共节点为大于接地电压的预定电压的电压。

公开(公告)号：US5631866A

公开(公告)日：1997-05-20

申请号：US444579

申请日：1995-05-19

Applicant: Tomoharu Oka ,  Yukinori Kodama ,  Katsumi Shigenobu

Inventor： Tomoharu Oka ,  Yukinori Kodama ,  Katsumi Shigenobu

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  G11C11/413 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C7/1072

Abstract: A synchronous DRAM is disclosed. The DRAM comprises an input buffer, a memory cell array, an output buffer, a signal transfer circuit, first and second latch circuits, and a controller. The input buffer receives an operation control signal supplied externally. The memory cell array has a plurality of memory cells for storing data. The output buffer outputs a data signal read from the memory cells. The signal transfer circuit reads a data signal from one of the memory cells in accordance with the operation control signal from the input buffer, and sends this read data signal to the output buffer. The first and second latch circuits, provided between the input buffer and the output buffer, latch the associated input signals in response to a clock signal. The controller controls the latching operation of the second latch circuit by delaying the clock signal input to the second latch circuit for a period of time from when the first latch circuit receives input from the input buffer to when the read data signal arrives at the second latch circuit.

Abstract translation: 公开了一种同步DRAM。 DRAM包括输入缓冲器，存储单元阵列，输出缓冲器，信号传输电路，第一和第二锁存电路以及控制器。 输入缓冲器接收外部提供的操作控制信号。 存储单元阵列具有用于存储数据的多个存储单元。 输出缓冲器输出从存储器单元读取的数据信号。 信号传送电路根据来自输入缓冲器的操作控制信号从一个存储单元读取数据信号，并将该读取的数据信号发送到输出缓冲器。 设置在输入缓冲器和输出缓冲器之间的第一和第二锁存电路响应于时钟信号锁存相关联的输入信号。 控制器通过将输入到第二锁存电路的时钟信号延迟一段时间，从第一锁存电路从输入缓冲器接收到从读取数据信号到达第二锁存器的时间段来控制第二锁存电路的锁存操作 电路。

公开(公告)号：US5327387A

公开(公告)日：1994-07-05

申请号：US971630

申请日：1992-11-05

Applicant: Akira Sugiura ,  Yukinori Kodama

Inventor： Akira Sugiura ,  Yukinori Kodama

IPC: G11C11/406 ,  G11C8/00

CPC classification number: G11C11/406

Abstract: A dynamic random access memory comprises a CBR refresh detection unit for detecting a commencement of a CBR refreshing cycle and a control signal generation unit for deactivating data output during the CBR cycle, both of the CBR refresh detection unit and the control signal generation unit being supplied with a /RAS signal and a /CAS signal simultaneously, wherein the dynamic random access memory further comprises a CBR refresh control unit supplied with an output of the CBR refresh detection unit and further with an output of the control signal generation unit for producing a control signal during the CBR refreshing cycle such that the control signal is produced in response to the leading edge of the /RAS signal and terminated in response to the trailing edge of the /CAS signal. Thereby, an output buffer circuit is controlled in response to the output of the control signal generation unit and the control signal of the CBR refresh control unit to set the output buffer circuit in the high impedance state during the CBR refreshing cycle.

Abstract translation: 动态随机存取存储器包括用于检测CBR刷新周期的开始的CBR刷新检测单元和用于停止在CBR周期期间输出的数据的控制信号生成单元，CBR刷新检测单元和控制信号生成单元都被提供 同时具有/ RAS信号和/ / CAS信号，其中动态随机存取存储器还包括CBR刷新控制单元，其被提供有CBR刷新检测单元的输出，并且还包括用于产生控制的控制信号生成单元的输出 信号，使得响应于/ RAS信号的前沿产生控制信号，并响应于/ CAS信号的后沿终止控制信号。 由此，响应于控制信号生成单元的输出和CBR刷新控制单元的控制信号控制输出缓冲器电路，以在CBR刷新周期期间将输出缓冲电路设置为高阻抗状态。

公开(公告)号：US5291447A

公开(公告)日：1994-03-01

申请号：US921155

申请日：1992-07-29

Applicant: Yukinori Kodama ,  Yasuhiro Fujii

Inventor： Yukinori Kodama ,  Yasuhiro Fujii

IPC: G11C11/409 ,  G11C7/06 ,  G11C7/10 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC classification number: G11C7/1096 ,  G11C7/065 ,  G11C7/1078

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells provided in the form of a matrix along a plurality of word lines and a plurality of pairs of bit lines, a plurality of sense amplifiers operatively connected to the plurality of pairs of bit lines, and a sense amplifier control unit operatively connected to the plurality of sense amplifiers. When one of the plurality of memory cells is selected and data writing is carried out to the selected memory cell, the sense amplifier control unit selectively inactivates only a sense amplifier corresponding to the selected memory cell among the plurality of sense amplifiers. Thus, it is possible to remove useless dissipation of write current in the data write operation to thereby decrease the dissipated power, while realizing a high speed write operation.

Abstract translation: 一种半导体存储器件包括存储单元阵列，该存储单元阵列包括沿着多条字线和多对位线以矩阵形式提供的多个存储器单元，多个读出放大器可操作地连接到多对 位线，以及可操作地连接到多个读出放大器的读出放大器控制单元。 当选择多个存储单元之一并对所选存储单元执行数据写入时，读出放大器控制单元仅选择性地使仅在多个读出放大器中与所选存储单元相对应的读出放大器失效。 因此，在实现高速写入操作的同时，可以在数据写入操作中消除写入电流的无用耗散，从而降低耗散功率。

公开(公告)号：US20060271807A1

公开(公告)日：2006-11-30

申请号：US11499721

申请日：2006-08-07

Applicant: Takaaki Suzuki ,  Yukinori Kodama ,  Sumie Kodama

Inventor： Takaaki Suzuki ,  Yukinori Kodama ,  Sumie Kodama

IPC: G06F1/04

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3253 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/172 ,  Y02D50/20

Abstract: A semiconductor integrated circuit is disclosed that operates in synch with a clock signal supplied from an external source, and by a voltage supplied by a power supply. The circuit includes a detection means for detecting that at least one of a frequency of the clock signal and the supply voltage is reduced, and an internal voltage reduction means for lowering an internal voltage of the semiconductor integrated circuit when the detection means detects that at least one of the frequency and the supply voltage is lowered.

Abstract translation: 公开了一种半导体集成电路，其与从外部源提供的时钟信号和由电源提供的电压同步工作。 该电路包括检测装置，用于检测时钟信号和电源电压的频率中的至少一个被降低;以及内部电压降低装置，用于当检测装置检测到至少一个时，降低半导体集成电路的内部电压 频率和电源电压之一降低。

公开(公告)号：US5767712A

公开(公告)日：1998-06-16

申请号：US892066

申请日：1997-07-14

Applicant: Yoshihiro Takemae ,  Masao Taguchi ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Takaaki Suzuki ,  Junji Ogawa ,  Atsushi Hatakeyama ,  Hirohiko Mochizuki ,  Hideaki Kawai

Inventor： Yoshihiro Takemae ,  Masao Taguchi ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Takaaki Suzuki ,  Junji Ogawa ,  Atsushi Hatakeyama ,  Hirohiko Mochizuki ,  Hideaki Kawai

IPC: G06F1/04 ,  G11C7/22 ,  H01L27/02 ,  H03K3/356 ,  H03K5/13 ,  H03K5/1534 ,  H03K5/24 ,  H03L7/00

CPC classification number: G06F1/04 ,  G11C7/22 ,  G11C7/222 ,  H03K3/356113 ,  H03K3/356156 ,  H03K5/133 ,  H03K5/1534 ,  H03K5/249

Abstract: A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

Abstract translation: 一种半导体器件包括：单脉冲发生电路，其在第一时钟信号的上升或下降定时产生具有预定脉冲宽度的单触发脉冲;周期时间测量电路，其测量第一时钟信号的周期时间 根据来自单触发脉冲发生电路的单触发脉冲输出，内部时钟发生电路，其基于由循环时间测量电路测量的周期时间和从单次脉冲发生电路输出的单次脉冲产生第二时钟信号; 射击脉冲发生电路。 第二时钟信号具有与第一时钟信号相同的周期时间，并且具有比第一时钟信号高一个特定时间的上升或下降定时，并且通过减去第一时钟的周期时间获得特定时间 信号，以及数据输出电路，其在从第二时钟信号的上升或下降定时之后的预定延迟时间之后输出数据。

公开(公告)号：US5592433A

公开(公告)日：1997-01-07

申请号：US643834

申请日：1996-05-07

Applicant: Hiroyoshi Tomita ,  Makoto Yanagisawa ,  Yukinori Kodama

Inventor： Hiroyoshi Tomita ,  Makoto Yanagisawa ,  Yukinori Kodama

IPC: G11C7/06 ,  G11C13/00

CPC classification number: G11C7/065

Abstract: A semiconductor memory device includes a memory cell array in which a number of sense amplifiers are provided, a plurality of segmented drive lines each connected to a group of sense amplifiers for driving the same, each of the segmented drive lines being formed of first and second drive line segments forming a pair, and a number of trunks for supplying electric power to the segmented drive lines. Each of the trunks includes a first conductor strip extending from a first side of the memory cell array toward a second side for connection to a plurality of the first drive line segments upon crossing the same, and a second conductor strip extending from the second side of the memory cell array toward the first side for connection to a plurality of the second drive line segments upon crossing the same. The first and second conductor strips have distal end parts having a reduced width and a mutually complementary shape, such that the first and second conductor strips are disposed to form a straight strip having a substantially constant width throughout the memory cell array.

Abstract translation: 一种半导体存储器件包括其中提供多个读出放大器的存储单元阵列，多个分段驱动线，每个驱动线连接到用于驱动读出放大器的一组读出放大器，每个分段驱动线由第一和第二 形成一对的驱动线段和用于向分段驱动线提供电力的多个中继线。 每个中继线包括从存储单元阵列的第一侧向第二侧延伸的第一导体条，用于在与第一驱动线段交叉时与多个第一驱动线段连接，第二导体条从第二侧延伸 所述存储单元阵列朝向所述第一侧，用于在与所述第二驱动线段交叉时连接到所述第二驱动线段。 第一和第二导体条具有具有减小的宽度和相互互补形状的远端部分，使得第一和第二导体条被设置成形成整个存储单元阵列具有基本恒定的宽度的直条。

公开(公告)号：US5353257A

公开(公告)日：1994-10-04

申请号：US16613

申请日：1993-02-11

Applicant: Makoto Yanagisawa ,  Yukinori Kodama

Inventor： Makoto Yanagisawa ,  Yukinori Kodama

IPC: G11C11/407 ,  G11C8/08 ,  G11C8/00

CPC classification number: G11C8/08

Abstract: In a word line driving circuit coupled to a word line of a memory cell array of a semiconductor memory device, a first transistor has a first terminal receiving an input signal based on a row address signal applied to the semiconductor memory device, a second terminal, and a control terminal receiving a first timing signal. A second transistor having a first terminal receiving a second timing signal, a second terminal connected to the word line, and a control terminal connected to the second terminal of the first transistor. A third transistor has a first terminal connected to the second terminal of the second transistor, a second terminal set at a predetermined potential, and a control terminal receiving a third timing signal. The first transistor has a threshold voltage less than that of at least one of the second and third transistors.

Abstract translation: 在耦合到半导体存储器件的存储单元阵列的字线的字线驱动电路中，第一晶体管具有基于施加到半导体存储器件的行地址信号接收输入信号的第一端子，第二端子， 以及接收第一定时信号的控制终端。 第二晶体管，具有接收第二定时信号的第一端子，连接到字线的第二端子以及连接到第一晶体管的第二端子的控制端子。 第三晶体管具有连接到第二晶体管的第二端子的第一端子，设置在预定电位的第二端子，以及接收第三定时信号的控制端子。 第一晶体管的阈值电压小于第二和第三晶体管中的至少一个的阈值电压。