公开(公告)号：US5978884A

公开(公告)日：1999-11-02

申请号：US880890

申请日：1997-06-23

Applicant: Shusaku Yamaguchi ,  Atsushi Hatakeyama ,  Masato Takita ,  Tadao Aikawa ,  Hirohiko Mochizuki

Inventor： Shusaku Yamaguchi ,  Atsushi Hatakeyama ,  Masato Takita ,  Tadao Aikawa ,  Hirohiko Mochizuki

IPC: G11C11/413 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C19/00 ,  G11C19/28 ,  G06F13/00 ,  G11C7/00

CPC classification number: G11C7/1048 ,  G11C19/00 ,  G11C19/28 ,  G11C7/1039

Abstract: A semiconductor memory device uses a wave pipeline system which can reduce a power consumption by reducing a current for charging a data bus between a memory core part and an output circuit. A single line data bus transmits read data output from the memory core part. A data bus drive circuit outputs the read read data to send to the single data bus. Each of a plurality of data latch circuits has a data input terminal connected to the data bus. A data input control circuit inputs the read data which is serially transmitted on the data bus to the data latch circuits in parallel in response to an operation of the data bus drive circuit. A data output control circuit outputs the latched read data in an order of latching by sequentially selecting outputs of the data latch circuits.

Abstract translation: 半导体存储器件使用波浪管线系统，其可以通过减少用于对存储器核心部分和输出电路之间的数据总线充电的电流来降低功耗。 单行数据总线发送从存储器核心部分输出的读取数据。 数据总线驱动电路输出读取的数据以发送到单个数据总线。 多个数据锁存电路中的每一个具有连接到数据总线的数据输入端子。 数据输入控制电路响应于数据总线驱动电路的操作，将数据总线上串行发送的读取数据并行输入数据锁存电路。 数据输出控制电路通过依次选择数据锁存电路的输出来以锁存顺序输出锁存的读取数据。

公开(公告)号：US5889725A

公开(公告)日：1999-03-30

申请号：US915332

申请日：1997-08-20

Applicant: Tadao Aikawa ,  Hirohiko Mochizuki ,  Atsushi Hatakeyama ,  Shusaku Yamaguchi ,  Koichi Nishimura

Inventor： Tadao Aikawa ,  Hirohiko Mochizuki ,  Atsushi Hatakeyama ,  Shusaku Yamaguchi ,  Koichi Nishimura

IPC: G11C11/413 ,  G11C8/10 ,  G11C8/00

CPC classification number: G11C8/10

Abstract: A semiconductor or memory device has a decoder circuit for decoding a plurality of external address signals. The external address signals include first and second external address signals. A first address buffer receives the first external address signals and outputs first internal address signals to first address lines. A second address buffer receives the second external address signals and outputs second internal address signals to second address lines. First predecoders have input terminals connected to the first address lines, and output first predecode signals to first predecode lines. Second predecoders have input terminals connected to the second address lines and output second predecode signals to second predecode lines. Main decoders have input terminals connected to the first predecode lines and the second predecode lines and output decode signals. The number of the first external address signals are greater than the number of the second external address signals. The second predecoders and the second predecode lines are provided at least in double in such a manner that inputs of the main decoders to be connected to each of the second predecode lines are equal in number to inputs of the main decoders to be connected to each of the first predecode lines. It is possible to shorten the transition time of predecode signals because of the same capacitive load of the predecoder circuit.

Abstract translation: 半导体或存储器件具有用于解码多个外部地址信号的解码器电路。 外部地址信号包括第一和第二外部地址信号。 第一地址缓冲器接收第一外部地址信号，并将第一内部地址信号输出到第一地址线。 第二地址缓冲器接收第二外部地址信号，并将第二内部地址信号输出到第二地址线。 第一预解码器具有连接到第一地址线的输入端，并将第一预解码信号输出到第一预解码线。 第二预解码器具有连接到第二地址线的输入端，并将第二预解码信号输出到第二预解码线。 主解码器具有连接到第一预解码线和第二预解码线并输出解码信号的输入端。 第一外部地址信号的数量大于第二外部地址信号的数量。 第二预解码器和第二预解码线以至少两个方式提供，使得要连接到每个第二预解码线的主解码器的输入数量等于要连接到每个的主解码器的输入 第一个预先代码行。 由于预解码器电路的容性负载相同，可以缩短预解码信号的转换时间。

公开(公告)号：US5663917A

公开(公告)日：1997-09-02

申请号：US510862

申请日：1995-08-03

Applicant: Tomoharu Oka ,  Hirohiko Mochizuki ,  Yasuhiro Fujii ,  Makoto Yanagisawa

Inventor： Tomoharu Oka ,  Hirohiko Mochizuki ,  Yasuhiro Fujii ,  Makoto Yanagisawa

IPC: G11C11/407 ,  G11C8/10 ,  H01L21/822 ,  H01L27/04 ,  H03K17/0812 ,  H03K17/10 ,  H03K19/00 ,  G11C8/00 ,  H03K5/00

CPC classification number: H03K17/102 ,  G11C8/10 ,  H03K17/08122

Abstract: A semiconductor circuit has a first transistor, a second transistor, a third transistor, and a fourth transistor. The first and fourth transistors are a first conduction type, and the second and third transistors are a second conduction type opposite to the first conduction type. The semiconductor circuit employs a first power supply line for supplying a first voltage, a second power supply line for supplying a second voltage, and a third power supply line for supplying a third voltage outside of the range determined by the first voltage and the second voltage. The first, second, and third transistors are connected in series between the second power supply line and the third power supply line, and the fourth transistor is connected between an input terminal and a control electrode of the first transistor.

Abstract translation: 半导体电路具有第一晶体管，第二晶体管，第三晶体管和第四晶体管。 第一和第四晶体管是第一导电类型，第二和第三晶体管是与第一导电类型相反的第二导电类型。 半导体电路采用用于提供第一电压的第一电源线，用于提供第二电压的第二电源线，以及用于将由第一电压和第二电压确定的范围之外的第三电压提供的第三电源线 。 第一，第二和第三晶体管串联连接在第二电源线和第三电源线之间，第四晶体管连接在第一晶体管的输入端和控制电极之间。

公开(公告)号：US4672372A

公开(公告)日：1987-06-09

申请号：US675628

申请日：1984-11-28

Applicant: Hatsuo Miyahara ,  Fumio Baba ,  Hirohiko Mochizuki

Inventor： Hatsuo Miyahara ,  Fumio Baba ,  Hirohiko Mochizuki

IPC: H03K19/0175 ,  G11C5/00 ,  G11C8/18 ,  G11C11/407 ,  G11C11/4074 ,  H03K5/13 ,  H03K19/00 ,  H03K19/003 ,  H03K19/096 ,  H04L7/00

CPC classification number: H03K5/133 ,  G11C5/00 ,  G11C8/18

Abstract: A semiconductor device having a dynamic circuit and a static circuit, wherein a clock signal, in synchronization with the operation of the static circuit, initiates the operation of the dynamic circuit. A delay circuit of a static type is provided to delay the clock signal and generate a delayed clock signal. The delayed clock signal initiates operation of one stage of the dynamic circuit. As a result, the final-operation timing of the dynamic circuit is substantially controlled by the delayed clock signal, thereby matching the operation of the dynamic circuit with the operation of the static circuit, regardless of the power supply voltage.

Abstract translation: 一种具有动态电路和静态电路的半导体器件，其中与静态电路的操作同步的时钟信号启动动态电路的操作。 提供静态延迟电路来延迟时钟信号并产生延迟的时钟信号。 延迟的时钟信号启动动态电路的一级的操作。 结果，动态电路的最终操作定时基本上被延迟的时钟信号控制，从而使动态电路的操作与静态电路的操作匹配，而与电源电压无关。

公开(公告)号：US5757226A

公开(公告)日：1998-05-26

申请号：US722934

申请日：1996-09-30

Applicant: Toyonobu Yamada ,  Tetsuya Endo ,  Takaaki Suzuki ,  Hirohiko Mochizuki ,  Masao Taguchi

Inventor： Toyonobu Yamada ,  Tetsuya Endo ,  Takaaki Suzuki ,  Hirohiko Mochizuki ,  Masao Taguchi

IPC: G05F1/46 ,  H01L20060101 ,  H01L27/105 ,  G05F1/10

CPC classification number: G05F1/465

Abstract: A semiconductor integrated circuit device includes a reference voltage generating circuit outputting a reference voltage from a step-up voltage, a step-up circuit stepping up the reference voltage within a range lower than an external power supply voltage and thus outputting the above step-up voltage, a step-down circuit stepping down the external power supply voltage and thus outputting a step-down voltage equal to the reference voltage, and an internal circuit receiving, as a power supply voltage thereof, the step-down voltage.

Abstract translation: 一种半导体集成电路器件，包括从升压电压输出参考电压的基准电压产生电路，在比外部电源电压低的范围内升压参考电压的升压电路，从而输出上述升压 电压，降压电路降低外部电源电压，从而输出等于参考电压的降压电压，内部电路作为其电源电压接收降压电压。

公开(公告)号：US5535169A

公开(公告)日：1996-07-09

申请号：US322564

申请日：1994-10-13

Applicant: Tetsuya Endo ,  Hirohiko Mochizuki ,  Yukinori Kodama ,  Yoshihiro Takemae

Inventor： Tetsuya Endo ,  Hirohiko Mochizuki ,  Yukinori Kodama ,  Yoshihiro Takemae

IPC: G11C11/406 ,  G11C11/407 ,  G11C8/00

CPC classification number: G11C11/406

Abstract: A semiconductor memory device includes a plurality of banks each having a memory cell array and sense amplifiers, a data input/output circuit and an address circuit. A first part of the device receives control signals from an outside of the semiconductor memory device and generates a refresh signal therefrom. A second part generates bank select signals in response to the refresh signal, the bank select signals being used to select the plurality of banks. A third part receives the bank select signals and generating latch enable signals therefrom, the latch enable signals driving the sense amplifiers provided in the plurality of banks. A refresh operation is carried out by activating the sense amplifiers by using the latch enable signals.

Abstract translation: 半导体存储器件包括多个存储单元，每个存储单元具有存储单元阵列和读出放大器，数据输入/输出电路和地址电路。 设备的第一部分从半导体存储器件的外部接收控制信号并从其产生刷新信号。 第二部分响应于刷新信号产生存储体选择信号，存储体选择信号用于选择多个存储体。 第三部分接收存储体选择信号并产生锁存使能信号，锁存器使能信号驱动设置在多个存储体中的读出放大器。 通过使用锁存使能信号来激活读出放大器来进行刷新操作。

公开(公告)号：US5319607A

公开(公告)日：1994-06-07

申请号：US793970

申请日：1991-11-18

Applicant: Yasuhiro Fujii ,  Hirohiko Mochizuki ,  Yukinori Kodama ,  Akira Sugiura

Inventor： Yasuhiro Fujii ,  Hirohiko Mochizuki ,  Yukinori Kodama ,  Akira Sugiura

IPC: G11C11/41 ,  G11C8/18 ,  G11C13/00

CPC classification number: G11C8/18

Abstract: The present invention relates to a semiconductor unit including a delay circuit used for an address transition detecting circuit in a storage, wherein a change of an address is detected and, accordingly, an access address in a memory cell is altered. The present invention aims at ensuring extending an address signal even though that of a short pulse width is provided, and at outputting an address transition detection signal of a predetermined pulse width, thereby stabilizing the operation of the circuit and improving its reliability. The present invention includes a second address extending circuit having a complementary transistor circuit, a capacitor connected to the output part of the complementary transistor circuit, and a resistor serially connected between a pair of complementary transistors. A signal generating circuit for outputs an address transition detection signal in response to a non-inverted address signal, an inverted address signal, and output of the first and the second address extending circuits.

Abstract translation: 本发明涉及包括用于存储器中的地址转换检测电路的延迟电路的半导体单元，其中检测到地址的变化，因此改变了存储单元中的存取地址。 本发明的目的在于确保扩展地址信号，即使提供短脉冲宽度，并且输出预定脉冲宽度的地址转换检测信号，从而稳定电路的操作并提高其可靠性。 本发明包括具有互补晶体管电路的第二地址扩展电路，连接到互补晶体管电路的输出部分的电容器和串联连接在一对互补晶体管之间的电阻器。 一种信号发生电路，用于响应于非反相地址信号，反相地址信号和第一和第二地址扩展电路的输出输出地址转变检测信号。

公开(公告)号：US4870617A

公开(公告)日：1989-09-26

申请号：US97558

申请日：1987-09-16

Applicant: Masao Nakano ,  Tsuyoshi Ohira ,  Hirohiko Mochizuki ,  Yukinori Kodama ,  Hidenori Nomura

Inventor： Masao Nakano ,  Tsuyoshi Ohira ,  Hirohiko Mochizuki ,  Yukinori Kodama ,  Hidenori Nomura

IPC: G11C11/409 ,  G11C5/06 ,  G11C7/10 ,  G11C11/401

CPC classification number: G11C5/063 ,  G11C7/1048

Abstract: A semiconductor memory device comprises a plurality of reset circuits connected to a data bus pair at different locations. Before each read operation, the reset circuits reset the data bus pair to a predetermined reset voltage. The resetting of the data bus pair is virtually unaffected by the distributed resistances and parasitic capacitances of the data bus pair, since the resetting is carried out at a plurality of locations on the data bus pair.

Abstract translation: 半导体存储器件包括在不同位置连接到数据总线对的多个复位电路。 在每次读取操作之前，复位电路将数据总线对复位到预定的复位电压。 数据总线对的复位实际上不受数据总线对的分布电阻和寄生电容的影响，因为复位是在数据总线对上的多个位置进行的。

公开(公告)号：US4413272A

公开(公告)日：1983-11-01

申请号：US183734

申请日：1980-09-03

Applicant: Hirohiko Mochizuki ,  Masao Nakano ,  Fumio Baba ,  Tomio Nakano ,  Yoshihiro Takemae

Inventor： Hirohiko Mochizuki ,  Masao Nakano ,  Fumio Baba ,  Tomio Nakano ,  Yoshihiro Takemae

IPC: G11C17/06 ,  G11C17/00 ,  G11C17/14 ,  G11C17/16 ,  H01L23/50 ,  H01L23/52 ,  H01L23/525 ,  H01L23/62

CPC classification number: G11C17/16 ,  H01L23/5256 ,  H01L23/62 ,  H01L2924/0002

Abstract: A semiconductor memory device has fuses coated with a protecting layer. The protecting layer is selectively etched to open windows so as to expose narrow center portions of the fuses. After the opening of the center windows, the fusing operation of the fuses is carried out to open a gap in the center window portion of the fuse material. In a preferred embodiment, another protective layer is then added to fill the gaps in the blown fuses.

Abstract translation: 半导体存储器件具有涂覆有保护层的保险丝。 选择性地蚀刻保护层以打开窗口，以便露出保险丝的中心部分。 在中心窗口打开之后，执行保险丝的熔合操作以在熔断体的中心窗部分中打开间隙。 在优选实施例中，然后添加另一保护层以填充熔断保险丝中的间隙。

公开(公告)号：US4382194A

公开(公告)日：1983-05-03

申请号：US213398

申请日：1980-12-05

Applicant: Masao Nakano ,  Fumio Baba ,  Hirohiko Mochizuki

Inventor： Masao Nakano ,  Fumio Baba ,  Hirohiko Mochizuki

IPC: H03K19/0185 ,  G11C5/14 ,  G11C11/4076 ,  G11C11/408 ,  H02M3/07 ,  H03K5/00 ,  H03K5/02 ,  H03K19/00 ,  H03K19/017 ,  H03K19/096 ,  H03K4/24 ,  H03K5/01

CPC classification number: H02M3/07 ,  G11C11/4076 ,  G11C11/4085 ,  G11C5/145 ,  H03K19/00 ,  H03K19/01707 ,  H03K19/01728 ,  H03K19/096 ,  H03K5/00

Abstract: A boosting circuit boosts a voltage of a load capacitor which is charged by a specific voltage. The boosting circuit comprises a boosting capacitor one end of which is connected to receive a clock signal, a charging circuit for charging the boosting capacitor, a gate circuit provided between the load capacitor and the other end of the boosting capacitor, and a gate control circuit for opening the gate circuit upon discharging of the charge of the boosting, that is controlled by the clock signal, to the load capacitor and for closing the gate circuit during discharging of the load capacitor. The charging circuit is provided separately from a circuit for supplying the specific voltage. The charges of the boosting capacitor under the control of the clock signal flow through the gate circuit to the load capacitor.

Abstract translation: 升压电路提高由特定电压充电的负载电容器的电压。 升压电路包括一个升压电容器，其一端连接以接收时钟信号，用于对升压电容器充电的充电电路，设置在负载电容器和升压电容器的另一端之间的门电路，以及栅极控制电路 用于在由时钟信号控制的放电电荷放电到负载电容器并且在负载电容器放电期间闭合栅极电路时打开门电路。 充电电路与用于提供特定电压的电路分开设置。 在时钟信号控制下的升压电容器的电荷通过栅极电路流到负载电容器。