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    Semiconductor device including memory cell having capacitor
    1.
    发明授权
    Semiconductor device including memory cell having capacitor 有权
    包括具有电容器的存储单元的半导体器件

    公开(公告)号：US08351247B2

    公开(公告)日：2013-01-08

    申请号：US12707044

    申请日：2010-02-17

    申请人： Hiroyuki Ogawa ,  Hiroyoshi Tomita ,  Masato Takita

    发明人： Hiroyuki Ogawa ,  Hiroyoshi Tomita ,  Masato Takita

    IPC分类号： G11C11/24

    CPC分类号： H01L27/0207 ,  G11C5/063 ,  G11C7/02 ,  G11C7/18 ,  G11C11/4097 ,  H01L27/1085 ,  H01L27/10885 ,  H01L27/10897

    摘要： A semiconductor device includes a semiconductor substrate; a memory cell array including a plurality of memory cells formed on the semiconductor substrate and arranged in a matrix in a first direction and a second direction on the surface of the semiconductor substrate; a plurality of sense amplifiers formed on the semiconductor substrate and including a first sense amplifier and a second sense amplifier; and a plurality of bit lines extending along the first direction above the memory cell array, and arranged side by side in the second direction, wherein the plurality of bit lines include a first bit line pair formed in a first wiring layer and a second bit line pair formed in a second wiring layer located above the first wiring layer.

    摘要翻译： 半导体器件包括半导体衬底; 存储单元阵列，包括形成在所述半导体衬底上并在所述半导体衬底的表面上沿第一方向和第二方向布置成矩阵的多个存储单元; 多个读出放大器，形成在半导体衬底上并包括第一读出放大器和第二读出放大器; 以及沿着存储单元阵列上方的第一方向延伸并沿第二方向并排布置的多个位线，其中多个位线包括形成在第一布线层中的第一位线对和第二位线 形成在位于第一布线层上方的第二布线层中。

    Semiconductor memory
    3.
    发明申请
    Semiconductor memory 有权
    半导体存储器

    公开(公告)号：US20060098504A1

    公开(公告)日：2006-05-11

    申请号：US11291777

    申请日：2005-12-02

    申请人： Masato Takita

    发明人： Masato Takita

    IPC分类号： G11C29/00

    CPC分类号： G11C11/406 ,  G11C11/40622 ,  G11C29/783

    摘要： A shift register includes plural latches corresponding to normal word lines of normal memory cell rows and a redundancy word line of a redundancy memory cell row, respectively, in order to sequentially activate any of the redundancy word line and the normal word lines upon every refresh request. An activation circuit activates any of the normal word lines and redundancy word line according to an output of the shift register. A first storing circuit stores in advance a defect address indicating a defective normal memory cell row. A first activation control circuit prohibits activation of a normal word line corresponding to the defect address stored in the first storing circuit when the output of the shift register indicates the normal word line.

    摘要翻译： 移位寄存器分别包括与正常存储单元行的正常字线对应的多个锁存器和冗余存储单元行的冗余字线，以便在每次刷新请求时依次激活冗余字线和正常字线中的任一个 。 激活电路根据移位寄存器的输出激活任何正常字线和冗余字线。 第一存储电路预先存储指示有缺陷的正常存储单元行的缺陷地址。 当移位寄存器的输出指示正常字线时，第一激活控制电路禁止激活对应于存储在第一存储电路中的缺陷地址的正常字线。

    Semiconductor integrated circuit
    4.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US06791354B2

    公开(公告)日：2004-09-14

    申请号：US10032465

    申请日：2002-01-02

    申请人： Kaoru Mori ,  Shinichi Yamada ,  Masato Takita

    发明人： Kaoru Mori ,  Shinichi Yamada ,  Masato Takita

    IPC分类号： G06F738

    CPC分类号： G11C11/4076 ,  G11C5/143 ,  G11C5/147 ,  G11C11/4074 ,  G11C2207/002 ,  G11C2207/2227

    摘要： A plurality of switching transistors is provided, each connects power supply terminals of a plurality of first circuit blocks to a power supply line, respectively. Among the first circuit blocks, the power supply terminals of the first circuit blocks operating at different timings are connected by an internal power supply line. A power supply control circuit simultaneously turns on the switching transistors connected to the internal power supply line, in response to operation(s) of at least any one of the first circuit blocks connected to the internal power supply line. Since the switching transistors can be shared among the first circuit blocks not operating simultaneously, operation speed of the first circuit blocks can be increased. Since a total size of the switching transistors can be made small, standby current can be decreased. Accordingly, a semiconductor integrated circuit operating at a high speed can be constituted without increasing the standby current.

    摘要翻译： 提供多个开关晶体管，每个将多个第一电路块的电源端分别连接到电源线。 在第一电路块中，在不同定时工作的第一电路的电源端子通过内部电源线连接。 响应于连接到内部电源线的至少任一个第一电路块的操作，电源控制电路同时接通连接到内部电源线的开关晶体管。 由于开关晶体管可以在不同时操作的第一电路块之间共享，所以可以增加第一电路块的操作速度。 由于可以使开关晶体管的总体尺寸小，所以可以降低待机电流。 因此，可以在不增加待机电流的情况下构成高速工作的半导体集成电路。

    Semiconductor integrated circuit and method of switching source potential of transistor in semiconductor integrated circuit
    6.
    发明授权
    Semiconductor integrated circuit and method of switching source potential of transistor in semiconductor integrated circuit 有权
    半导体集成电路中半导体集成电路和晶体管的源极电位切换方法

    公开(公告)号：US06605963B2

    公开(公告)日：2003-08-12

    申请号：US09412590

    申请日：1999-10-05

    申请人： Ayako Kitamoto ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Hideki Kanou ,  Kuninori Kawabata ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

    发明人： Ayako Kitamoto ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Hideki Kanou ,  Kuninori Kawabata ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

    IPC分类号： H03K19185

    CPC分类号： H03K19/0013 ,  H03K3/356113 ,  H03K17/102 ,  H03K19/00361 ,  H03K2217/0036

    摘要： A semiconductor integrated circuit, comprising a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit by a combination of a plurality of transistors, is disclosed. Among a plurality of the transistors of the circuit unit, the source potential of at least one transistor adapted to turn off during the standby period of the circuit unit is changed. Preferably, the semiconductor integrated circuit is configured to reduce the sub-threshold current flowing between the source and the drain of at least one transistor adapted to turn off during the standby period of the circuit unit by changing the source potential at a timing based on the standby period of the circuit unit in such a manner that a predetermined bias voltage is applied between the gate and the source of the transistor. A method of switching the source potential of at least one transistor in the semiconductor integrated circuit having the configuration described above is also disclosed.

    摘要翻译： 公开了一种半导体集成电路，其包括具有预定功能的电路单元，例如通过多个晶体管的组合的电平移位器电路或驱动晶体管电路。 在电路单元的多个晶体管中，改变了在电路单元的待机期间适于关断的至少一个晶体管的源极电位。 优选地，半导体集成电路被配置为减少在电路单元的待机时段期间流过至少一个晶体管的源极和漏极之间的亚阈值电流，其在基于 以使得在晶体管的栅极和源极之间施加预定的偏置电压的方式使电路单元的待机时段。 还公开了一种在具有上述结构的半导体集成电路中切换至少一个晶体管的源极电位的方法。

    Semiconductor integrated circuit
    7.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US06538493B2

    公开(公告)日：2003-03-25

    申请号：US10021059

    申请日：2001-12-19

    申请人： Toru Koga ,  Shinichi Yamada ,  Masato Takita

    发明人： Toru Koga ,  Shinichi Yamada ,  Masato Takita

    IPC分类号： H03K301

    CPC分类号： H01L27/088 ,  H03K19/0016

    摘要： A first transistor is turned on during operation of a circuit block, to connect a substrate of the transistor to a first substrate voltage line. A second transistor is turned on during non-operation of the circuit block, to connect the substrate of the transistor to a second substrate voltage line. ON resistance of the second transistor is higher than that of the first transistor. A source-to-substrate voltage of the transistor being not in operation is set to be higher than that of the transistor being in operation. When a semiconductor integrated circuit switches from the operation state to the non-operation state, its substrate voltage changes gradually to a second substrate voltage. Charging/discharging currents of the substrate voltage can be dispersed so that it is possible to suppress current consumption in shifting from the operation state to the non-operation state and reduce a standby current in the non-operation state.

    摘要翻译： 在电路块的操作期间，第一晶体管导通，以将晶体管的衬底连接到第一衬底电压线。 在电路块的非操作期间，第二晶体管导通，以将晶体管的衬底连接到第二衬底电压线。 第二晶体管的导通电阻高于第一晶体管的导通电阻。 晶体管的未工作的源极到衬底的电压被设定为高于正在工作的晶体管的电压。 当半导体集成电路从操作状态切换到非操作状态时，其基板电压逐渐变化到第二基板电压。 可以分散基板电压的充放电电流，从而可以抑制从工作状态转移到非工作状态的电流消耗，并且可以减少非工作状态下的待机电流。

    Semiconductor memory having sub-select lines cross-connected to sub-decoders
    9.
    发明授权
    Semiconductor memory having sub-select lines cross-connected to sub-decoders 失效
    具有与子解码器交叉连接的子选择线的半导体存储器

    公开(公告)号：US06188597B1

    公开(公告)日：2001-02-13

    申请号：US09540877

    申请日：2000-03-31

    申请人： Masato Takita ,  Shinichi Yamada ,  Masato Matsumiya

    发明人： Masato Takita ,  Shinichi Yamada ,  Masato Matsumiya

    IPC分类号： G11C506

    CPC分类号： G11C29/848 ,  G11C8/04 ,  G11C8/10 ,  G11C8/14 ,  G11C11/4087 ,  H01L27/10897

    摘要： In a semiconductor memory, sub-decoders in two adjacent sub-decoder groups are mirror-arranged with respect to the boundary between the two blocks. Sub-select lines are cross-connected to the sub-decoders in one sub-decoder group. This permits all sub-select lines connected to the two adjacent sub-decoder groups to be sequentially selected in a certain direction in accordance with a sequentially incremented address. Even when shift redundancy processing is performed, the order of selection of these sub-select lines does not reverse itself owing to the mirror arrangement.

    摘要翻译： 在半导体存储器中，两个相邻子解码器组中的子解码器相对于两个块之间的边界被镜像布置。 子选择线在一个子解码器组中与子解码器交叉连接。 这允许根据顺序增加的地址在连接到两个相邻子解码器组的所有子选择线在特定方向上顺序选择。 即使执行了移位冗余处理，这些子选择线的选择顺序也不会由于镜子的排列而自身反转。