公开(公告)号：US20100321983A1

公开(公告)日：2010-12-23

申请号：US12718819

申请日：2010-03-05

申请人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

发明人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

IPC分类号： G11C11/24 ,  G11C5/14

CPC分类号： G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

摘要翻译： 半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平 在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。 此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量 当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量 存储单元阵列。 此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡 电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。

公开(公告)号：US07079443B2

公开(公告)日：2006-07-18

申请号：US10631752

申请日：2003-08-01

申请人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

发明人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

IPC分类号： G11C8/08

CPC分类号： G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

摘要翻译： 半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平 在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。 此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量 当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量 存储单元阵列。 此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡 电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。

公开(公告)号：US06618320B2

公开(公告)日：2003-09-09

申请号：US10316121

申请日：2002-12-11

申请人： Masatomo Hasegawa ,  Kaoru Mori ,  Masato Matsumiya

发明人： Masatomo Hasegawa ,  Kaoru Mori ,  Masato Matsumiya

IPC分类号： G11C800

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072

摘要： A semiconductor memory device is provided with a clock generation circuit that generates a first clock that has the same frequency and phase as an external clock, and a second clock that has the same frequency as the external clock but a phase a quarter phase shifted, and the first clock and the second clock are supplied to the two DDR-DRAMs as clocks so that the two DDR-DRAMs can operate in a state of being a quarter phase shifted from each other. A data output section outputs data respectively for time periods corresponding to a quarter phase from points a fixed phase behind the leading edge and the trailing edge of the first or the second clock and brings a data output circuit into a high impedance state for other time periods.

摘要翻译： 半导体存储器件设置有产生与外部时钟具有相同频率和相位的第一时钟的时钟产生电路和具有与外部时钟相同频率但是相位四分之一相位偏移的第二时钟，以及 第一时钟和第二时钟作为时钟提供给两个DDR DRAM，使得两个DDR-DRAM可以在相互偏移的四分之一相的状态下操作。 数据输出部分分别从第一或第二时钟的前沿和后沿之后的固定相位的点分别输出对应于四分之一相位的时间段的数据，并将数据输出电路在其他时间段内变为高阻抗状态 。

公开(公告)号：US06201378B1

公开(公告)日：2001-03-13

申请号：US09301203

申请日：1999-04-28

申请人： Satoshi Eto ,  Masato Matsumiya ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

发明人： Satoshi Eto ,  Masato Matsumiya ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

IPC分类号： G05F316

CPC分类号： G11C11/4074 ,  G11C5/147 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/4099

摘要： A semiconductor integrated circuit producing a given output voltage includes first and second operational amplifiers, and first and second transistors. The first and second operational amplifiers detect a voltage difference between a voltage applied to an input terminal and at least one reference voltage. The first and second transistors are turned ON or turned OFF according to the levels of voltages output from the first and second operational amplifiers. The first operational amplifier receives the output voltage at the input terminal. When the level of the output voltage becomes lower than the reference voltage, the first operational amplifier allows the first transistor to operate so as to raise the output voltage. In contrast, the second operational amplifier receives the output voltage at the input terminal. When the level of the output voltage exceeds the reference voltage, the second operational amplifier allows the second transistor to operate so as to lower the output voltage.

摘要翻译： 产生给定输出电压的半导体集成电路包括第一和第二运算放大器以及第一和第二晶体管。 第一和第二运算放大器检测施加到输入端的电压与至少一个参考电压之间的电压差。 根据从第一和第二运算放大器输出的电压的电平，第一和第二晶体管导通或截止。 第一个运算放大器在输入端接收输出电压。 当输出电压的电平变得低于参考电压时，第一运算放大器允许第一晶体管工作，以便提高输出电压。 相反，第二运算放大器在输入端接收输出电压。 当输出电压的电平超过参考电压时，第二运算放大器允许第二晶体管工作，以降低输出电压。

公开(公告)号：US6111795A

公开(公告)日：2000-08-29

申请号：US342059

申请日：1999-06-29

申请人： Masato Takita ,  Masato Matsumiya ,  Masatomo Hasegawa ,  Toshimi Ikeda

发明人： Masato Takita ,  Masato Matsumiya ,  Masatomo Hasegawa ,  Toshimi Ikeda

IPC分类号： G11C11/407 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/408 ,  G11C7/00

CPC分类号： G11C8/08 ,  G11C11/4076 ,  G11C11/4087 ,  G11C8/10 ,  G11C8/18

摘要： On one hand, a row address is provided via a buffer gate to a row address register 11, and its output is provided via a complementary signal generation circuit 15 and a predecoder 16 to a word decoder 17A. On the other hand, in response to an issuance of an activate command a control signal AS1 is provided via a delay circuit 14 to the clock input CK of the row address register 11 as a strobe signal AS2, and AS2 is provided, to reduce timing margin, via a delay circuit 20A to the strobe signal input of the predecoder 16 as a strobe signal S2. S2 is provided via a delay circuit 20B to the strobe signal input of the word decoder 17A having RS flip-flops 2301 to 2332 or latch circuits. Each of the latch circuits consists of a NOR gate having a set input and a reset input and another NOR gate having an input coupled to receive the output of the former NOR gate and another set input to receive a multiple selection signal which is common for all the latch circuits in word decoders.

摘要翻译： 一方面，通过缓冲器将行地址提供给行地址寄存器11，并且其输出经由互补信号生成电路15和预解码器16提供给字解码器17A。 另一方面，响应于激活命令的发出，控制信号AS1经由延迟电路14提供给行地址寄存器11的时钟输入CK作为选通信号AS2，并且提供AS2以减少定时 通过延迟电路20A将预解码器16的选通信号输入作为选通信号S2。 S2经由延迟电路20B提供给具有RS触发器2301至2332或锁存电路的字解码器17A的选通信号输入。 每个锁存电路由具有设定输入和复位输入的NOR门组成，另一NOR门具有耦合以接收前NOR门的输出和另一组输入的输入，以接收对于所有者共同的多选择信号 字解码器中的锁存电路。

公开(公告)号：US07733105B2

公开(公告)日：2010-06-08

申请号：US12139288

申请日：2008-06-13

申请人： Yoshiaki Nozaki ,  Hiroshi Kawamura ,  John Kevin Twynam ,  Masatomo Hasegawa

发明人： Yoshiaki Nozaki ,  Hiroshi Kawamura ,  John Kevin Twynam ,  Masatomo Hasegawa

IPC分类号： G01R31/02

CPC分类号： G01R1/06766 ,  G01R31/2621

摘要： In a voltage clamp circuit, a normally-on type field-effect transistor having a negative threshold voltage has a drain connected to an input node, a source connected to an output node and grounded via a resistance element, and a gate supplied with an output voltage of a variable direct-current power supply. When a voltage at the output node becomes higher than a clamping voltage because of voltage drop of the resistance element, the field-effect transistor is tuned off. Accordingly, the output voltage is limited to be at most the clamping voltage. Thus, a response speed is higher than those of conventional voltage clamp circuits using diodes or the like.

摘要翻译： 在电压钳位电路中，具有负阈值电压的常导型场效应晶体管具有连接到输入节点的漏极，连接到输出节点的源极，并且经由电阻元件接地，以及提供有输出的栅极 可变直流电源的电压。 当输出节点的电压由于电阻元件的电压降而变得高于钳位电压时，场效应晶体管被关断。 因此，输出电压被限制为至多钳位电压。 因此，响应速度高于使用二极管等的常规电压钳位电路的响应速度。

公开(公告)号：US20060098523A1

公开(公告)日：2006-05-11

申请号：US11313963

申请日：2005-12-22

申请人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

发明人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

IPC分类号： G11C8/00

CPC分类号： G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

摘要翻译： 半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平 在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。 此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量 当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量 存储单元阵列。 此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡 电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。

公开(公告)号：US06198686B1

公开(公告)日：2001-03-06

申请号：US09613583

申请日：2000-07-10

申请人： Masato Takita ,  Masato Matsumiya ,  Masatomo Hasegawa ,  Toshimi Ikeda

发明人： Masato Takita ,  Masato Matsumiya ,  Masatomo Hasegawa ,  Toshimi Ikeda

IPC分类号： G11C800

CPC分类号： G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4087

摘要： On one hand, a row address is provided via a buffer gate to a row address register 11, and its output is provided via a complementary signal generation circuit 15 and a predecoder 16 to a word decoder 17A. On the other hand, in response to an issuance of-an activate command a control signal AS1 is provided via a delay circuit 14 to the clock input CK of the row address register 11 as a strobe signal AS2, and AS2 is provided, to reduce timing margin, via a delay circuit 20A to the strobe signal input of the predecoder 16 as a strobe signal S2. S2 is provided via a delay circuit 20B to the strobe signal input of the word decoder 17A having RS flip-flops 2301 to 2332 or latch circuits. Each of the latch circuits consists of a NOR gate having a set input and a reset input and another NOR gate having an input coupled to receive the output of the former NOR gate and another set input to receive a multiple selection signal which is common for all the latch circuits in word decoders.

摘要翻译： 一方面，通过缓冲器将行地址提供给行地址寄存器11，并且其输出经由互补信号生成电路15和预解码器16提供给字解码器17A。 另一方面，响应于发出激活命令，控制信号AS1经由延迟电路14提供给行地址寄存器11的时钟输入CK作为选通信号AS2，并且提供AS2以减少 定时裕度，经由延迟电路20A到预解码器16的选通信号输入作为选通信号S2。 S2经由延迟电路20B提供给具有RS触发器2301至2332或锁存电路的字解码器17A的选通信号输入。 每个锁存电路由具有设定输入和复位输入的NOR门组成，另一NOR门具有耦合以接收前NOR门的输出和另一组输入的输入，以接收对于所有者共同的多选择信号 字解码器中的锁存电路。

公开(公告)号：US6147919A

公开(公告)日：2000-11-14

申请号：US274245

申请日：1999-03-23

申请人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Hideki Kanou ,  Ayako Kitamoto ,  Toru Koga ,  Yuki Ishii ,  Akira Kikutake ,  Yuichi Uzawa

发明人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Hideki Kanou ,  Ayako Kitamoto ,  Toru Koga ,  Yuki Ishii ,  Akira Kikutake ,  Yuichi Uzawa

IPC分类号： H01L27/10 ,  G11C7/06 ,  G11C7/12 ,  G11C7/02

CPC分类号： G11C7/06 ,  G11C7/12

摘要： A semiconductor memory has memory cells arranged in arrays, direct-type sense amplifiers arranged in each column of the memory cells, for writing and reading data to and from a memory cell to be accessed, column selection lines for selecting sense amplifiers that are in a column that involves the memory cell to be accessed, write-only column selection lines for selecting sense amplifiers that are in a row that involves the memory cell to be accessed if the memory cell is accessed to write data thereto, and local drivers. The sense amplifiers are grouped, in each row, into sense amplifier blocks. The write-only column selection lines consist of first selection lines for selecting sense amplifier blocks that are in the row that involves the memory cell to be accessed for data write and second selection lines for selecting sense amplifiers that are contained in the selected sense amplifier blocks. The local drivers apply a selection signal to the second selection lines according to a selection signal from the first selection lines. The write-only column selection lines are controlled by signals that are used to control the sense amplifiers.

摘要翻译： 半导体存储器具有排列成阵列的存储单元，布置在每个存储单元列中的直接型读出放大器，用于向要被访问的存储单元写入数据和从存储单元读取数据;列选择线，用于选择读取放大器 涉及要访问的存储器单元的列，只读列选择线，用于选择存储单元被访问以涉及要访问的存储器单元的行的读出放大器以写入数据，以及本地驱动器。 读出放大器在每行中分组成读出放大器模块。 只写列选择线由用于选择读入放大器块的第一选择线组成，所述读出放大器块包括要被存取的存储单元以进行数据写入，第二选择线用于选择包含在所选择的读出放大器块中的读出放大器 。 本地驱动器根据来自第一选择线的选择信号向第二选择线施加选择信号。 只写列选择线由用于控制读出放大器的信号控制。

公开(公告)号：US5671239A

公开(公告)日：1997-09-23

申请号：US588693

申请日：1996-01-19

申请人： Masaaki Higashitani ,  Masatomo Hasegawa

发明人： Masaaki Higashitani ,  Masatomo Hasegawa

IPC分类号： G06F11/10 ,  G11C17/00 ,  G11C29/00 ,  G11C29/44

CPC分类号： G06F11/1008 ,  G11C29/44 ,  G11C29/82

摘要： A memory device for storing data of a multi-bit structure in a plurality of memory cell blocks has a parity cell block having the same structure as the memory cell block. If read data contains an error bit, this error bit is corrected by an EOR calculation of correct bits and a parity bit. The address of an error bit is written in a defective cell memory made of fuses for example. In the case of a flash memory, a parity calculation and a parity data write operation are performed at the same time when data is written.

摘要翻译： 用于在多个存储单元块中存储多位结构的数据的存储器件具有与存储单元块相同结构的奇偶校验单元块。 如果读取数据包含错误位，则通过正确位和奇偶校验位的EOR计算校正该错误位。 错误位的地址被写入例如由保险丝制成的故障单元存储器中。 在闪存的情况下，在写入数据的同时执行奇偶校验计算和奇偶校验数据写入操作。