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    Dynamic random access memory having a stacked fin capacitor with reduced fin thickness
    2.
    发明授权
    Dynamic random access memory having a stacked fin capacitor with reduced fin thickness 失效
    动态随机存取存储器，其具有减小翅片厚度的堆叠鳍式电容器

    公开(公告)号：US5661340A

    公开(公告)日：1997-08-26

    申请号：US141691

    申请日：1993-10-26

    Applicant: Taiji Ema ,  Masaaki Higashitani ,  Toshimi Ikeda ,  Michiari Kawano ,  Hiroshi Nomura ,  Masaya Katayama ,  Masahiro Kuwamura

    Inventor： Taiji Ema ,  Masaaki Higashitani ,  Toshimi Ikeda ,  Michiari Kawano ,  Hiroshi Nomura ,  Masaya Katayama ,  Masahiro Kuwamura

    IPC: H01L21/8242 ,  H01L27/108 ,  H01L23/02 ,  H01L21/265

    CPC classification number: H01L27/10852 ,  H01L27/10817

    Abstract: A method for fabricating a dynamic random access memory comprises the steps of forming a diffusion region in a semiconductor substrate, providing an insulation layer on the semiconductor substrate, forming a contact hole in the insulation layer to expose the diffusion region at the contact hole, depositing a semiconductor layer on the insulation layer in the amorphous state such that the semiconductor layer establishes an intimate contact with the exposed diffusion region via the contact hole, patterning the semiconductor layer to form a capacitor electrode, depositing a dielectric film on the capacitor electrode such that said dielectric film covers the capacitor electrode; and depositing a semiconductor material to form an opposing electrode such that the opposing electrode buries the capacitor electrode underneath while establishing an intimate contact with the dielectric film that covers the capacitor electrode.

    Abstract translation: 一种用于制造动态随机存取存储器的方法，包括以下步骤：在半导体衬底中形成扩散区，在半导体衬底上提供绝缘层，在绝缘层上形成接触孔，露出接触孔处的扩散区，沉积 在绝缘层上形成非晶状态的半导体层，使得半导体层经由接触孔与暴露的扩散区域形成紧密接触，构图半导体层以形成电容器电极，在电容器电极上沉积电介质膜，使得 所述电介质膜覆盖电容器电极; 以及沉积半导体材料以形成相对的电极，使得相对电极将电容器电极埋在下面，同时与覆盖电容器电极的电介质膜形成紧密接触。

    Method of liquid treatment of micro-structures comprising structural members liable to be bent
    3.
    发明授权
    Method of liquid treatment of micro-structures comprising structural members liable to be bent 失效
    微结构液体处理方法，包括易于弯曲的结构构件

    公开(公告)号：US5652167A

    公开(公告)日：1997-07-29

    申请号：US83371

    申请日：1993-06-29

    Applicant: Motoo Nakano ,  Hiroshi Nomura ,  Masaya Katayama ,  Toshimi Ikeda ,  Fumihiko Inoue ,  Junichi Ishikawa ,  Masahiro Kuwamura

    Inventor： Motoo Nakano ,  Hiroshi Nomura ,  Masaya Katayama ,  Toshimi Ikeda ,  Fumihiko Inoue ,  Junichi Ishikawa ,  Masahiro Kuwamura

    IPC: B81B3/00 ,  H01L21/02 ,  H01L21/20 ,  H01L21/306 ,  H01L21/70

    CPC classification number: B81B3/0005 ,  B81C1/0092 ,  H01L21/02063 ,  H01L28/87 ,  Y10T428/24744 ,  Y10T428/24942 ,  Y10T428/26 ,  Y10T428/8305

    Abstract: Micro-structures comprising at least a structural member, which is liable to be bent under an external force and formed so as to leave a space between the member and another member liable to be bent and/or other rigid component, are successfully treated using a treating liquid, without suffering permanent deformation resulting from the use of the treating liquid, by removing the micro-structures from the liquid to an environment having a pressure less than the atmospheric pressure; or displacing the micro-structures from the treating liquid to another treating liquid having a smaller surface tension than that of the former liquid, and then removing the micro-structures from the latter liquid; or drying the micro-structures removed from the treating liquid by exposing the same to vapor of a liquid having a smaller surface tension than that of the treating liquid; or removing the micro-structures from the treating liquid to the atmosphere, and drying them using an energy beam of high intensity or an ultrasonic wave. Micro-structures are also disclosed which comprise at least a member liable to be bent but are capable of avoiding permanent deformation of the member resulting from a treatment using a liquid.

    Abstract translation: 至少包括结构构件的微结构，其在外力下容易弯曲并且形成为在构件和易于弯曲的另一构件和/或其他刚性构件之间留下空间，成功地使用 处理液体，而不会由于使用处理液而导致永久变形，通过将微结构从液体移除到具有小于大气压力的压力的环境中; 或将微结构从处理液体移位到具有比前者液体小的表面张力的另一处理液，然后从后一液体中除去微结构; 或者通过将从处理液中除去的微结构暴露于具有比处理液的表面张力小的液体的蒸汽，来干燥微结构; 或将微结构从处理液中除去至大气，并使用高强度能量束或超声波干燥它们。 还公开了微结构，其包括至少一个易于弯曲的构件，但是能够避免由使用液体的处理引起的构件的永久变形。

    Multi-value nonvolatile semiconductor memory device equipped with reference cell and load balancing circuit
    4.
    发明授权
    Multi-value nonvolatile semiconductor memory device equipped with reference cell and load balancing circuit 有权
    配有参考电池和负载平衡电路的多值非易失性半导体存储器件

    公开(公告)号：US07307885B2

    公开(公告)日：2007-12-11

    申请号：US11063999

    申请日：2005-02-24

    Applicant: Toshimi Ikeda ,  Atsushi Hatakeyama ,  Nobutaka Taniguchi ,  Akira Kikutake ,  Kuninori Kawabata ,  Atsushi Takeuchi

    Inventor： Toshimi Ikeda ,  Atsushi Hatakeyama ,  Nobutaka Taniguchi ,  Akira Kikutake ,  Kuninori Kawabata ,  Atsushi Takeuchi

    IPC: G11C16/28

    CPC classification number: G11C16/28 ,  G11C7/14 ,  G11C2207/002

    Abstract: A nonvolatile semiconductor memory device includes a plurality of memory cells holding memory cell information, a plurality of bit lines connected to the plurality of memory cells, the plurality of bit lines including a first bit line conected to a selected one of the plurality of memory cells and a plurality of second bit lines connected to non-selected memory cells, a plurality of reference cells supplying different reference currents respectively, and a read-out circuit, wherein, when reading the memory cell information, the read-out circuit is coupled to the first bit line connected to the selected memory cell and coupled to one of the plurality of reference cells through one of the plurality of second bit lines connected to the non-selected memory cells.

    Abstract translation: 非易失性半导体存储器件包括保持存储单元信息的多个存储器单元，连接到多个存储器单元的多个位线，多个位线包括与多个存储器单元中选择的一个存储单元相连的第一位线 以及连接到未选择的存储器单元的多个第二位线，分别提供不同参考电流的多个参考单元和读出电路，其中当读取存储单元信息时，读出电路耦合到 所述第一位线连接到所选择的存储器单元，并且通过连接到所述未选择的存储器单元的所述多个第二位线之一耦合到所述多个参考单元中的一个。

    Memory device
    6.
    发明申请
    Memory device 失效
    内存设备

    公开(公告)号：US20050141306A1

    公开(公告)日：2005-06-30

    申请号：US11069940

    申请日：2005-03-03

    Applicant: Atsushi Hatakeyama ,  Toshimi Ikeda ,  Nobutaka Taniguchi ,  Akira Kikutake ,  Kuninori Kawabata ,  Atsushi Takeuchi

    Inventor： Atsushi Hatakeyama ,  Toshimi Ikeda ,  Nobutaka Taniguchi ,  Akira Kikutake ,  Kuninori Kawabata ,  Atsushi Takeuchi

    IPC: G11C5/06 ,  G11C16/06 ,  G11C16/28

    CPC classification number: G11C16/28

    Abstract: A memory device has a data line (DATA-BUS) for connection to a memory cell, a reference line (Reference-BUS) for reference, a precharge circuit (101), a load circuit (102), and an amplifier circuit (103). The precharge circuit is connected to the data line and the reference line and configured to precharge the data line and the reference line. The load circuit is connected to the data line and the reference line and configured to apply a first constant current to the data line and apply a second constant current which is smaller than the first constant current to the reference line. The amplification circuit is connected to the data line and the reference line and configured to amplify a differential voltage between the data line and the reference line.

    Abstract translation: 存储器件具有用于连接到存储单元的数据线（DATA-BUS），用于参考的参考线（Reference-BUS），预充电电路（101），负载电路（102）和放大器电路（103） ）。 预充电电路连接到数据线和参考线，并配置为对数据线和参考线进行预充电。 负载电路连接到数据线和参考线，并配置为向数据线施加第一恒定电流，并将比第一恒定电流小的第二恒定电流施加到参考线。 放大电路连接到数据线和参考线，并被配置为放大数据线与参考线之间的差分电压。

    Method of manufacturing helical gears by compacting powder materials
    7.
    发明授权
    Method of manufacturing helical gears by compacting powder materials 失效
    通过压实粉末材料制造斜齿轮的方法

    公开(公告)号：US06383447B1

    公开(公告)日：2002-05-07

    申请号：US09610474

    申请日：2000-07-05

    Applicant: Toyoshige Nakata ,  Tadaaki Shimada ,  Tatsuhiro Iio ,  Toshimasa Fujita ,  Toshimi Ikeda

    Inventor： Toyoshige Nakata ,  Tadaaki Shimada ,  Tatsuhiro Iio ,  Toshimasa Fujita ,  Toshimi Ikeda

    IPC: B22F302

    CPC classification number: B30B11/02 ,  B22F5/08

    Abstract: An intermediary die 10 is provided with inner circumferential helical teeth r, a lower punch 7 is provided with outer circumferential helical teeth p, and an upper punch 8 is provided with outer circumferential helical teeth q, respectively. When the intermediary die 10, the lower punch 7 and the upper punch 8 all engage to manufacture helical gears by compacting powdered materials, lateral displacement (phase displacement) of a phase guide 11 which is adapted to engage with the upper outer punch 8a, is forcibly corrected to allow it to return to its original position, from the time when the load of the upper outer punch 8a is reduced to when the intermediary die 10 is released. There is also provided an escape surface on the pressing surface of the upper outer punch 8a. The escape surface is designed to reduce the slide contact force developed on a compacted product Ga when the upper outer punch 8a and the compacted product Ga are respectively displaced in a lateral direction.

    Abstract translation: 中间模具10设置有内周螺旋齿r，下冲头7设置有外周螺旋齿p，上冲头8分别设置有外周螺旋齿q。 当中间模具10，下冲头7和上冲头8都接合以通过压实粉末材料制造斜齿轮时，适于与上外冲头8a接合的相导向件11的横向位移（相位移动）是 从上部外冲头8a的负载减小到中间模具10被释放的时刻被强制地修正为允许其返回到其原始位置。 另外，在上外侧冲头8a的按压面上设置有脱离面。 逃逸面被设计成当上部外冲头8a和压制产品Ga分别沿横向方向移位时，减小在压制产品Ga上产生的滑动接触力。

    Memory device having row decoder
    8.
    发明授权
    Memory device having row decoder 有权
    具有行解码器的存储器件

    公开(公告)号：US06198686B1

    公开(公告)日：2001-03-06

    申请号：US09613583

    申请日：2000-07-10

    Applicant: Masato Takita ,  Masato Matsumiya ,  Masatomo Hasegawa ,  Toshimi Ikeda

    Inventor： Masato Takita ,  Masato Matsumiya ,  Masatomo Hasegawa ,  Toshimi Ikeda

    IPC: G11C800

    CPC classification number: G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4087

    Abstract: On one hand, a row address is provided via a buffer gate to a row address register 11, and its output is provided via a complementary signal generation circuit 15 and a predecoder 16 to a word decoder 17A. On the other hand, in response to an issuance of-an activate command a control signal AS1 is provided via a delay circuit 14 to the clock input CK of the row address register 11 as a strobe signal AS2, and AS2 is provided, to reduce timing margin, via a delay circuit 20A to the strobe signal input of the predecoder 16 as a strobe signal S2. S2 is provided via a delay circuit 20B to the strobe signal input of the word decoder 17A having RS flip-flops 2301 to 2332 or latch circuits. Each of the latch circuits consists of a NOR gate having a set input and a reset input and another NOR gate having an input coupled to receive the output of the former NOR gate and another set input to receive a multiple selection signal which is common for all the latch circuits in word decoders.

    Abstract translation: 一方面，通过缓冲器将行地址提供给行地址寄存器11，并且其输出经由互补信号生成电路15和预解码器16提供给字解码器17A。 另一方面，响应于发出激活命令，控制信号AS1经由延迟电路14提供给行地址寄存器11的时钟输入CK作为选通信号AS2，并且提供AS2以减少 定时裕度，经由延迟电路20A到预解码器16的选通信号输入作为选通信号S2。 S2经由延迟电路20B提供给具有RS触发器2301至2332或锁存电路的字解码器17A的选通信号输入。 每个锁存电路由具有设定输入和复位输入的NOR门组成，另一NOR门具有耦合以接收前NOR门的输出和另一组输入的输入，以接收对于所有者共同的多选择信号 字解码器中的锁存电路。

    Levenson type phase shift photomask and manufacture method of semiconductor device using such photomask
    9.
    发明授权
    Levenson type phase shift photomask and manufacture method of semiconductor device using such photomask 失效
    莱文森型相移光掩模和使用这种光掩模的半导体器件的制造方法

    公开(公告)号：US5994004A

    公开(公告)日：1999-11-30

    申请号：US19743

    申请日：1998-02-06

    Applicant: Yasuko Tabata ,  Satoru Asai ,  Toshimi Ikeda ,  Masato Matsumiya

    Inventor： Yasuko Tabata ,  Satoru Asai ,  Toshimi Ikeda ,  Masato Matsumiya

    IPC: G03F1/30 ,  G03F1/68 ,  H01L21/027 ,  G03F9/00

    CPC classification number: G03F1/30

    Abstract: A photomask has a plurality of transparent regions defined in an opaque region and classified into first and second groups. Each of the transparent regions belonging to one of the first and second groups is provided with a phase shifter, so that the phase of light transmitted through the transparent region belonging to the first group becomes different from the phase of light transmitted through the transparent region belonging to the second group. The photomask includes: a pair of first transparent regions belonging to the first group and including linear portions disposed in parallel, a virtual straight line interconnecting one ends of the first transparent regions intersecting at a right angle with the extension direction of the linear portions; and a second transparent region belonging to the second group and disposed at the center between, and in parallel to, the linear portions of the pair of first transparent regions, the second transparent region including a linear thickportion and a linear thin portion, the linear thin portion being disposed in an area between the pair of first transparent regions and continuously coupled to the linear thick portion, and a connection portion between the thick and thin portions being indented from the virtual straight line toward the area between the pair of first transparent regions.

    Abstract translation: 光掩模具有限定在不透明区域中并被分类为第一和第二组的多个透明区域。 属于第一组和第二组中的一个的透明区域中的每一个设置有移相器，使得透过属于第一组的透明区域的光的相位与透过透明区域的光的相位不同 到第二组。 光掩模包括：属于第一组的一对第一透明区域，并且包括平行设置的直线部分，将与直线部分的延伸方向成直角相交的第一透明区域的一端相互连接的虚拟直线; 以及属于第二组的第二透明区域，并且设置在一对第一透明区域的直线部分之间并且平行于中心，第二透明区域包括线性​​厚度部分和线状薄部分，线性薄片 部分设置在一对第一透明区域之间的区域中并且连续地连接到线状厚部分，并且厚部分和薄部分之间的连接部分从假想直线向着该对第一透明区域之间的区域缩进。

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