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    Semiconductor memory device capable of driving non-selected word lines to first and second potentials
    1.
    发明申请
    Semiconductor memory device capable of driving non-selected word lines to first and second potentials 失效
    能够将未选择的字线驱动到第一和第二电位的半导体存储器件

    公开(公告)号：US20060098523A1

    公开(公告)日：2006-05-11

    申请号：US11313963

    申请日：2005-12-22

    申请人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

    发明人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

    IPC分类号： G11C8/00

    CPC分类号： G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

    摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

    摘要翻译： 半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平 在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。 此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量 当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量 存储单元阵列。 此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡 电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。

    Semiconductor memory device based on dummy-cell method
    2.
    发明授权
    Semiconductor memory device based on dummy-cell method 失效
    基于虚拟单元法的半导体存储器件

    公开(公告)号：US06868023B2

    公开(公告)日：2005-03-15

    申请号：US10656374

    申请日：2003-09-08

    申请人： Masato Takita ,  Shinichi Yamada ,  Masato Matsumiya

    发明人： Masato Takita ,  Shinichi Yamada ,  Masato Matsumiya

    IPC分类号： G11C11/403 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4099 ,  G11C7/00 ,  G11C7/02

    CPC分类号： G11C7/062 ,  G11C7/14 ,  G11C11/4091 ,  G11C11/4099

    摘要： A semiconductor memory device includes a plurality of bit line pairs, each of which includes a first bit line and a second bit line, a plurality of memory cells which are coupled to said first bit line, and store electric charge in capacitors, a dummy cell which is coupled to a second bit line, and is charged with a predetermined potential, a sense amplifier which amplifies a potential difference between the first bit line and the second bit line, and a control circuit which charges said dummy cell with the predetermined potential only for a fixed time period.

    摘要翻译： 半导体存储器件包括多个位线对，每个位线对包括第一位线和第二位线，耦合到所述第一位线的多个存储器单元，并将电荷存储在电容器中;虚拟单元 其被耦合到第二位线，并且被充电为预定电位;放大器，用于放大第一位线和第二位线之间的电位差;以及控制电路，其对所述虚设单元充电仅具有预定电位 固定时间段。

    Semiconductor memory device with overdriven sense amplifier and stabilized power-supply circuit of source follower type
    5.
    发明授权
    Semiconductor memory device with overdriven sense amplifier and stabilized power-supply circuit of source follower type 有权
    半导体存储器件，具有过驱动读出放大器和源极跟随器类型的稳定电源电路

    公开(公告)号：US06262930B1

    公开(公告)日：2001-07-17

    申请号：US09612281

    申请日：2000-07-07

    申请人： Kaoru Mori ,  Masato Matsumiya ,  Ayako Kitamoto ,  Shinichi Yamada ,  Yuki Ishii ,  Hideki Kanou ,  Masato Takita

    发明人： Kaoru Mori ,  Masato Matsumiya ,  Ayako Kitamoto ,  Shinichi Yamada ,  Yuki Ishii ,  Hideki Kanou ,  Masato Takita

    IPC分类号： G11C700

    CPC分类号： G11C7/06

    摘要： To reduce current consumption, there is provided a circuit for each bank, comprising selection circuits 26 through 28 each for selecting either a normal supply voltage Vii or a higher supply voltage Vjj as a supply voltage VH0 in response to a selection control signals SC0 and *SC0, a selection control circuit 22 for generating the signals SC0 and *SC0 to make the selection circuits select Vii when a bank activation signal BRAS0 is inactive and Vjj for a predetermined period in response to activation of BRAS0, and sense amplifier driving circuits 111 through 113 for supplying the ground voltage and VH0 to the sense amplifier rows in response to activation of sense amplifier control signals. To stabilize the output voltage Vii of the power supply circuit having a NMOS transistor, the drain electrode, gate and source electrodes of which are at VCC, VG and approximately Vii=VG−Vth, where Vth is the threshold voltage of the NMOS transistor 45, a leak circuit is employed. The leak circuit has a NMOS transistor connected between Vii and ground. Wasteful power consumption by the current flowing to the leak circuit is negligibly small, e.g. 1 to 10 &mgr;A, and the variation of the supply voltage Vii reduces effectively.

    摘要翻译： 为了减少电流消耗，为每个存储体提供一个电路，其中包括选择电路26至28，每个选择电路26至28用于响应于选择控制信号SC0和*选择正常电源电压Vii或较高电源电压Vjj作为电源电压VH0， SC0，用于产生信号SC0和* SC0的选择控制电路22，以使得当存储体激活信号BRAS0不活动时选择电路选择Vii，并响应于BRAS0的激活而在预定时间段内选择Vjj，读出放大器驱动电路111通过 113，用于响应于感测放大器控制信号的激活而将接地电压和VH0提供给读出放大器行。 为了稳定具有NMOS晶体管的电源电路的输出电压Vii，其漏电极，栅极和源电极处于VCC，VG和大约Vii = VG-Vth，其中Vth是NMOS晶体管45的阈值电压 ，采用泄漏电路。 泄漏电路具有连接在Vii和地之间的NMOS晶体管。 通过流向泄漏电路的电流浪费的功率消耗可忽略不计，例如， 1〜10μA，电源电压Vii的变化有效降低。

    Semiconductor memory device with overdriven sense amplifier and stabilized power-supply circuit of source follower type
    6.
    发明授权
    Semiconductor memory device with overdriven sense amplifier and stabilized power-supply circuit of source follower type 有权
    半导体存储器件，具有过驱动读出放大器和源极跟随器类型的稳定电源电路

    公开(公告)号：US6115316A

    公开(公告)日：2000-09-05

    申请号：US342060

    申请日：1999-06-29

    申请人： Kaoru Mori ,  Masato Matsumiya ,  Ayako Kitamoto ,  Shinichi Yamada ,  Yuki Ishii ,  Hideki Kanou ,  Masato Takita

    发明人： Kaoru Mori ,  Masato Matsumiya ,  Ayako Kitamoto ,  Shinichi Yamada ,  Yuki Ishii ,  Hideki Kanou ,  Masato Takita

    IPC分类号： G11C7/06 ,  G11C8/00

    CPC分类号： G11C7/06

    摘要： To reduce current consumption, there is provided a circuit for each bank, comprising selection circuits 26 through 28 each for selecting either a normal supply voltage Vii or a higher supply voltage Vjj as a supply voltage VH0 in response to a selection control signals SC0 and *SC0, a selection control circuit 22 for generating the signals SC0 and *SC0 to make the selection circuits select Vii when a bank activation signal BRAS0 is inactive and Vjj for a predetermined period in response to activation of BRAS0, and sense amplifier driving circuits 111 through 113 for supplying the ground voltage and VH0 to the sense amplifier rows in response to activation of sense amplifier control signals. To stabilize the output voltage Vii of the power supply circuit having a NMOS transistor, the drain electrode, gate and source electrodes of which are at VCC, VG and approximately Vii=VG-Vth, where Vth is the threshold voltage of the NMOS transistor 45, a leak circuit is employed. The leak circuit has a NMOS transistor connected between Vii and ground. Wasteful power consumption by the current flowing to the leak circuit is negligibly small, e.g. 1 to 10 .mu.A, and the variation of the supply voltage Vii reduces effectively.

    摘要翻译： 为了减少电流消耗，为每个存储体提供一个电路，其中包括选择电路26至28，每个选择电路26至28用于响应于选择控制信号SC0和*选择正常电源电压Vii或较高电源电压Vjj作为电源电压VH0， SC0，用于产生信号SC0和* SC0的选择控制电路22，以使得当存储体激活信号BRAS0不活动时选择电路选择Vii，并响应于BRAS0的激活而在预定时间段内选择Vjj，读出放大器驱动电路111通过 113，用于响应于感测放大器控制信号的激活而将接地电压和VH0提供给读出放大器行。 为了稳定具有NMOS晶体管的电源电路的输出电压Vii，其漏电极，栅极和源电极处于VCC，VG和大约Vii = VG-Vth，其中Vth是NMOS晶体管45的阈值电压 ，采用泄漏电路。 泄漏电路具有连接在Vii和地之间的NMOS晶体管。 通过流向泄漏电路的电流浪费的功率消耗可忽略不计，例如， 1至10μA，并且电源电压Vii的变化有效降低。

    Semiconductor memory, and memory access method
    7.
    发明授权
    Semiconductor memory, and memory access method 有权
    半导体存储器和存储器存取方法

    公开(公告)号：US06421292B1

    公开(公告)日：2002-07-16

    申请号：US09892748

    申请日：2001-06-28

    申请人： Ayako Kitamoto ,  Masato Matsumiya ,  Shinichi Yamada ,  Masato Takita

    发明人： Ayako Kitamoto ,  Masato Matsumiya ,  Shinichi Yamada ,  Masato Takita

    IPC分类号： G11C700

    CPC分类号： G11C7/1006 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2211/4062

    摘要： In the semiconductor memory, a refresh signal is generated and the refresh operation is performed based on the refresh signal. Parity is generated when data is written and the generated parity is stored. When the refresh operation and a usual data read or write operation overlap, data in a memory cell which cannot be read because the refresh operation is given priority is determined based on the parity. Data which cannot be written because the refresh operation is given priority is held temporarily in a write data buffer. When the refresh operation is not overlapped for the usual data read or write operation, the data held in the write data buffer is rewritten in a corresponding memory cell.

    摘要翻译： 在半导体存储器中，产生刷新信号，并且基于刷新信号执行刷新操作。 当写入数据并生成产生的奇偶校验时产生奇偶校验。 当刷新操作和通常的数据读取或写入操作重叠时，基于奇偶校验来确定由于刷新操作被赋予优先级而不能读取的存储器单元中的数据。 由于刷新操作被赋予优先级而不能写入的数据暂时保存在写入数据缓冲器中。 当刷新操作对于通常的数据读取或写入操作不重叠时，保持在写入数据缓冲器中的数据被重写在相应的存储器单元中。

    Semiconductor memory
    8.
    发明授权
    Semiconductor memory 失效

    公开(公告)号：US06404692B1

    公开(公告)日：2002-06-11

    申请号：US09539615

    申请日：2000-03-31

    申请人： Masato Takita ,  Yuichi Uzawa ,  Shinichi Yamada ,  Masato Matsumiya

    发明人： Masato Takita ,  Yuichi Uzawa ,  Shinichi Yamada ,  Masato Matsumiya

    IPC分类号： G11C700

    CPC分类号： G11C7/1072 ,  G11C8/12 ,  G11C11/4085 ,  G11C11/4087

    摘要： A semiconductor memory selects desired one of word lines, which belong to banks each including a memory cell array, on the basis of a main WD select signal (mwd) and sub-WD select signals (swdx and swdz) determined in accordance with an address. The main WD select signal is a pulse signal. A latch circuit latches, for a predetermined time, the state of the sub-WD select signals having changed on the basis of state changes of the main WD select signal. This allows the banks to share the main WD select signal. Since a main WD signal generator is thus shared by the banks, the area of a chip can be reduced.

    Semiconductor integrated circuit and semiconductor memory device including overdriving sense amplifier
    9.
    发明授权
    Semiconductor integrated circuit and semiconductor memory device including overdriving sense amplifier 有权
    半导体集成电路和包括过驱动读出放大器的半导体存储器件

    公开(公告)号：US06236605B1

    公开(公告)日：2001-05-22

    申请号：US09501269

    申请日：2000-02-09

    申请人： Kaoru Mori ,  Ayako Kitamoto ,  Masato Matsumiya ,  Masato Takita ,  Shinichi Yamada ,  Koichi Nishimura ,  Atsushi Hatakeyama

    发明人： Kaoru Mori ,  Ayako Kitamoto ,  Masato Matsumiya ,  Masato Takita ,  Shinichi Yamada ,  Koichi Nishimura ,  Atsushi Hatakeyama

    IPC分类号： G11C700

    CPC分类号： G11C7/08 ,  G11C5/025 ,  G11C5/14 ,  G11C7/065 ,  G11C11/4074 ,  G11C11/4091 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/065

    摘要： A transistor of a driver in the semiconductor integrated circuit according to the present invention has its gate connected to a controlling circuit, and has its drain connected to a sense amplifier. The controlling circuit supplies the gate of the transistor with a gate-to-source voltage exceeding or below other power supply voltages. The drain-to-source resistance of the transistor in the on state becomes sufficiently lower as compared with that in the case of supplying the power supply voltages between the gate and source of the transistor. Accordingly, the amplifying speed of the sense amplifier is heightened without altering the sense amplifier and the driver. Besides, the amplifying speed of the sense amplifier is heightened without raising the power supply voltage which supplies the carriers to the driver. The semiconductor memory device according to the present invention switches the driving supply voltage for the sense amplifier from the first supply voltage, to the second supply voltage lower than the first voltage. The timing at which the first supply voltage is switched to the second supply voltage is controlled in accordance with the voltage on a dummy bit line which is driven by a monitoring sense amplifier. Accordingly, even when the driving speed of the sense amplifier using the overdriving system has fluctuated due to the fluctuation of the first supply voltage, the driving supply voltage of the sense amplifier can be always switched to the second supply voltage at the appropriate timing.

    摘要翻译： 根据本发明的半导体集成电路中的驱动器的晶体管的栅极连接到控制电路，并且其漏极连接到读出放大器。 控制电路为晶体管的栅极提供超过或低于其他电源电压的栅极至源极电压。 与在晶体管的栅极和源极之间提供电源电压的情况相比，导通状态下的晶体管的漏极 - 源极电阻变得足够低。 因此，增强了读出放大器的放大速度，而不改变读出放大器和驱动器。 此外，增强读出放大器的放大速度，而不会提高向驱动器提供载波的电源电压。 根据本发明的半导体存储器件将读出放大器的驱动电源电压从第一电源电压切换到低于第一电压的第二电源电压。 根据由监视读出放大器驱动的虚拟位线上的电压来控制第一电源电压切换到第二电源电压的定时。 因此，即使当使用过驱动系统的读出放大器的驱动速度由于第一电源电压的波动而波动时，也可以在适当的定时将读出放大器的驱动电源电压始终切换到第二电源电压。