公开(公告)号：US06836163B2

公开(公告)日：2004-12-28

申请号：US10678937

申请日：2003-10-03

申请人： James R. Spehar

发明人： James R. Spehar

IPC分类号： H03L700

CPC分类号： H03K5/151 ,  H03K19/00323 ,  H03K2005/00052 ,  H04L25/0272

摘要： The invention provides an improved differential output structure with minimal skew and introduces less process variations. According to one embodiment of the invention, a differential output structure is provided and comprises an input line, an output driver and a sync circuit. The input line includes first and second paths. The first path has an input end for receiving input signals. The first path also has an output end and includes at least one driving element. The second path has an input end operably coupled to the input end of the first path for receiving the input signals. The second path also has an output end. The output driver is operably coupled to the output ends of the first and second paths and is configured to provide differential outputs. The sync circuit is operably coupled between the first and second paths and is configured to synchronize the speed of signals traveling on the two paths.

摘要翻译： 本发明提供了一种改进的差分输出结构，具有最小的偏差并且引入较少的工艺变化。 根据本发明的一个实施例，提供了差分输出结构并且包括输入线，输出驱动器和同步电路。 输入线包括第一和第二路径。 第一路径具有用于接收输入信号的输入端。 第一路径还具有输出端并包括至少一个驱动元件。 第二路径具有可操作地耦合到第一路径的输入端的输入端，用于接收输入信号。 第二条路径也有一个输出端。 输出驱动器可操作地耦合到第一和第二路径的输出端，并且被配置为提供差分输出。 同步电路可操作地耦合在第一和第二路径之间，并且被配置为使在两条路径上行进的信号的速度同步。

公开(公告)号：US06828865B2

公开(公告)日：2004-12-07

申请号：US10197021

申请日：2002-07-17

申请人： Shinichi Yamane ,  Seiji Watanabe

发明人： Shinichi Yamane ,  Seiji Watanabe

IPC分类号： H03L700

CPC分类号： H03L7/085 ,  H03L7/0807 ,  H03L7/087 ,  H03L7/0898 ,  H04L7/0087

摘要： This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functions, i.e., phase and duty adjustments for binarized data, the phase comparison with one edge is performed only at the phase adjustment by means of a phase-locked loop circuit 33 having an edge switching means 4 which controls the phase comparator 1. The phase comparator 1 inputs the binarized and a bit synchronous clock, and switches the output between a comparison result with one edge, i.e., a rising edge or a falling edge of binarized data, and a comparison result with both edges.

公开(公告)号：US06828834B2

公开(公告)日：2004-12-07

申请号：US10328603

申请日：2002-12-24

申请人： Stefano Sivero ,  Riccardo Riva-Reggiori ,  Lorenzo Bedarida

发明人： Stefano Sivero ,  Riccardo Riva-Reggiori ,  Lorenzo Bedarida

IPC分类号： H03L700

CPC分类号： H03K17/223 ,  G05F1/465

摘要： A power-on management system for an on-chip voltage down-converter, monitoring both external and internal voltage supplies to independently determine when both supplies have reached minimum levels for proper operation of on-chip circuitry. The power-on management system supplies output signals that: control the discharge of the internal supply nodes at the initiation of power-on; force the active mode of the voltage down-converter; and deactivate a fast local voltage reference on completion of power-on.

摘要翻译： 用于片上电压下变频器的上电管理系统，可监控外部和内部电压电源，以独立确定两个电源何时达到最小电平，以正常工作片上电路。 上电管理系统提供输出信号：在开机时控制内部供电节点的放电; 强制降压转换器的主动模式; 并在完成上电时停用快速本地电压基准。

公开(公告)号：US06825730B1

公开(公告)日：2004-11-30

申请号：US10403606

申请日：2003-03-31

申请人： Runhua Sun

发明人： Runhua Sun

IPC分类号： H03L700

CPC分类号： H03L7/0898 ,  H03L7/0896

摘要： A charge-pump and a method are provided for conditioning the phase detector output in a phase-locked loop (PLL). The method comprises: accepting a pair of differential phase detector (PD) output signals (up/upb and dn/dnb); connecting each pair of differential PD outputs to first and second charge-pump differential sections; supplying differential charge-pump outputs (Vout+/Vout−) in response to the pair of differential PD output signals; and, disconnecting the charge-pump differential section outputs from the loop filter inputs when the PD differential outputs (up/dn and upb/dnb) are equal. In some aspects, supplying differential charge-pump outputs (Vout+/Vout−) in response to the pair of differential PD output signals includes sourcing a first current through the first charge-pump differential section and sourcing a second current through the second charge-pump differential section. Then, the method further comprises maintaining the first current equal to the second current.

摘要翻译： 提供电荷泵和方法来调节锁相环（PLL）中的相位检测器输出。 该方法包括：接收一对差分相位检测器（PD）输出信号（up / upb和dn / dnb）; 将每对差分PD输出连接到第一和第二电荷泵差动部分; 响应一对差分PD输出信号，提供差分电荷泵输出（Vout + / Vout-）; 并且当PD差分输出（up / dn和upb / dnb）相等时，断开来自环路滤波器输入的电荷泵差分部分输出。 在一些方面，响应于一对差分PD输出信号供应差分电荷泵输出（Vout + / Vout-）包括通过第一电荷泵差分部分提供第一电流并且通过第二电荷泵 差分段。 然后，该方法还包括保持第一电流等于第二电流。

公开(公告)号：US06825728B1

公开(公告)日：2004-11-30

申请号：US10356449

申请日：2003-01-31

申请人： Paul F. Beard ,  Eric Mitchell

发明人： Paul F. Beard ,  Eric Mitchell

IPC分类号： H03L700

CPC分类号： H03L7/193

摘要： A method for generating parameters for adjusting the frequency of a VCO. A desired carrier frequency may be based off the output of the VCO. The method determines parameters that are operable to adjust the frequency of the VCO, based on the channel number. The channel number may be input into combinatorial logic to determine the parameters. Offsets, which may be scaled, may be added to the channel number before determining the parameters, wherein the frequency of the VCO is further adjusted based on the offset(s). A first parameter may be operable to select a frequency scalar in a circuit with the VCO. A second parameter may be operable to generate a feedback signal for adjusting the frequency of the VCO.

摘要翻译： 一种用于产生用于调节VCO的频率的参数的方法。 期望的载波频率可以基于VCO的输出。 该方法基于通道号确定可操作以调整VCO的频率的参数。 信道号可以被输入到组合逻辑中以确定参数。 可以缩放的偏移量可以在确定参数之前添加到通道号，其中基于偏移进一步调整VCO的频率。 第一参数可以用于在VCO的电路中选择频率标量。 第二参数可以用于产生用于调整VCO的频率的反馈信号。

公开(公告)号：US06822692B2

公开(公告)日：2004-11-23

申请号：US09944162

申请日：2001-08-30

申请人： Andreas Menkhoff

发明人： Andreas Menkhoff

IPC分类号： H03L700

CPC分类号： H03H17/0294

摘要： Digital filter for filtering a digital input signal with a variable filter length (l), it being possible to switch over the filter length (l) of the digital filter (8) as a function of a variable input clock frequency (fin) of the digital input signal without the ratio between the input clock frequency (fin) and an output clock frequency (fout) of the filtered digital output signal which is output by the digital filter (8) changing.

摘要翻译： 用于以可变滤波器长度（l）对数字输入信号进行滤波的数字滤波器，可以作为可变输入时钟频率（fin）的函数切换数字滤波器（8）的滤波器长度（l） 没有输入时钟频率（fin）与由数字滤波器（8）输出的滤波数字输出信号的输出时钟频率（fout）之间的比率发生变化的数字输入信号。

公开(公告)号：US06819150B1

公开(公告)日：2004-11-16

申请号：US09957144

申请日：2001-09-19

申请人： Handiono Santosa ,  Simon Kim ,  Sheng Hung Wang

发明人： Handiono Santosa ,  Simon Kim ,  Sheng Hung Wang

IPC分类号： H03L700

CPC分类号： G06F1/3237 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  H03L7/00 ,  H04W52/029 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D70/122

摘要： A power reduction device which includes a first clocking device for generating a first clocking signal, a second clocking device for generating a second clocking signal, a synchronizer device for receiving the first and second clocking signals and being responsive to a first select signal and to a second control signal wherein upon receipt of either of the select or control signals, the synchronizing device generating a synchronized signal without a glitch therefrom wherein the synchronized signal corresponding to either the first or second clocking signals.

摘要翻译： 一种功率降低装置，包括用于产生第一时钟信号的第一时钟装置，用于产生第二时钟信号的第二时钟装置，用于接收第一和第二时钟信号并响应于第一选择信号的同步装置， 第二控制信号，其中在接收到选择或控制信号中的任何一个时，所述同步装置产生不产生毛刺的同步信号，其中对应于第一或第二计时信号的同步信号。

公开(公告)号：US06816018B1

公开(公告)日：2004-11-09

申请号：US10198902

申请日：2002-07-19

申请人： Bruce L. Trumbo ,  John C. LeVieux

发明人： Bruce L. Trumbo ,  John C. LeVieux

IPC分类号： H03L700

CPC分类号： H03L7/087

摘要： In a phase-locked loop, multiple input clock references can each connect to a different interface card. Each interface card can include a phase comparator portion of a phase-locked loop. The phase comparators can produce a phase error signal for a phase-locked loop. One or more of the phase error signals can be transmitted across a bus, such as a time division multiplexed bus, to a system card. The system card can include a controlled oscillator portion of the phase-locked loop. The output of the system card can then sent back to one or more of the interface cards to complete the phase-locked loop.

摘要翻译： 在锁相环中，多个输入时钟参考可以连接到不同的接口卡。 每个接口卡可以包括锁相环的相位比较器部分。 相位比较器可以产生锁相环的相位误差信号。 一个或多个相位误差信号可以通过诸如时分多路复用总线的总线传输到系统卡。 系统卡可以包括锁相环的受控振荡器部分。 然后，系统卡的输出可以发送回一个或多个接口卡，以完成锁相环。

公开(公告)号：US06803830B2

公开(公告)日：2004-10-12

申请号：US10177196

申请日：2002-06-21

申请人： Bernd Scheffler

发明人： Bernd Scheffler

IPC分类号： H03L700

CPC分类号： H03L7/10 ,  H03L7/099 ,  H03L7/18

摘要： A phase-locked loop (10) comprises a voltage-controlled oscillator (12) to which a control voltage is applied as produced by a phase/frequency detector (22) as a function of the difference between the frequency (fref) of a reference signal and the output frequency (fvco) of the voltage controlled oscillator (12) and the oscillator contains as a frequency-influencing circuit element a varactor (14) whose capacitance value can be varied over a fine adjustment range by the control voltage for altering the output frequency. A variable capacitance (18) is provided which can be connected in parallel to the varactor (14) when there is a change in the frequency (fref) of the reference signal, the value of this capacitance (18) being adjustable as a function of the control voltage output by the phase/frequency detector (22).

摘要翻译： 锁相环（10）包括压控振荡器（12），由相位/频率检测器（22）产生的施加控制电压的压控振荡器作为参考频率（fref）之间的差异的函数 信号和压控振荡器（12）的输出频率（fvco）和振荡器包含作为频率影响电路元件的变容二极管（14），其变容二极管（14）的电容值可以通过控制电压在微调范围内变化，以改变 输出频率。 提供了可变电容（18），当可变参考信号的频率（fref）时，该可变电容（18）可以与变容二极管（14）并联连接，该电容（18）的值可调整为 由相位/频率检测器（22）输出的控制电压。

公开(公告)号：US06798298B2

公开(公告)日：2004-09-28

申请号：US09993588

申请日：2001-11-16

申请人： Paul C. Davis ,  Irving G. Post

发明人： Paul C. Davis ,  Irving G. Post

IPC分类号： H03L700

CPC分类号： H03L7/0896

摘要： A balancing circuit and method of operation thereof for use with a circuit having first and second complementary drivers exhibiting different current gain characteristics. In one embodiment, the balancing circuit includes a sensing subcircuit that provides a correction signal indicating a first current gain characteristic of the first driver. The balancing circuit also includes a compensation subcircuit that generates a current gain compensation signal to the first driver to substantially match a second current gain characteristic of the second driver based on the correction signal.

摘要翻译： 一种用于与具有不同电流增益特性的第一和第二互补驱动器的电路一起使用的平衡电路及其操作方法。 在一个实施例中，平衡电路包括检测子电路，其提供指示第一驱动器的第一电流增益特性的校正信号。 平衡电路还包括补偿子电路，其产生到第一驱动器的电流增益补偿信号，以基于校正信号基本匹配第二驱动器的第二电流增益特性。