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公开(公告)号：US06819146B2
公开(公告)日：2004-11-16
申请号：US10272941
申请日：2002-10-18
申请人： In-Young Chung
发明人： In-Young Chung
IPC分类号： H03K522
CPC分类号： H04L25/45 , H03K3/356113 , H03K3/35613 , H03K5/023 , H03K5/08 , H03K5/2481 , H03K5/249
摘要： A data receiver and data receiving method using signal integration and capable of reducing high-frequency noises generated upon high-speed data detection. The data receiver includes an integration amplification circuit receiving at least two differential reference signals and N (where N is a natural number greater than zero) data signals and integrating and amplifying differences between the at least two differential reference signals and one or more of the N data signals and outputting at least first differential signals and at least second differential signals and a detection amplification circuit for receiving the at least first differential signals and the at least second differential signals and detecting a difference between the at least first differential signals and the at least second differential signals to detect a value of one or more of the N data signals The data receiver and data receiving method, using signal integration, can reduce high-frequency noises generated when data is detected at a high speed. The data receiver and data receiving method, where signals inputted through two reference signal lines and one data line are integrated and amplified to detect data, provide accurate data detection at a high speed using differential signaling, irrespective of changes in a process, voltage level, or temperature.
摘要翻译： 一种使用信号积分并能够减少高速数据检测时产生的高频噪声的数据接收器和数据接收方法。 数据接收机包括一个积分放大电路，接收至少两个差分参考信号，N（其中N是大于0的自然数）数据信号，并且积分和放大至少两个差分参考信号与N中的一个或多个之间的差值 数据信号并输出至少第一差分信号和至少第二差分信号;以及检测放大电路，用于接收所述至少第一差分信号和所述至少第二差分信号，并且检测所述至少第一差分信号与所述至少第二差分信号之间的差异 用于检测N个数据信号中的一个或多个的值的第二差分信号。使用信号积分的数据接收器和数据接收方法可以减少在高速检测数据时产生的高频噪声。 数据接收器和数据接收方法，其中通过两个参考信号线和一个数据线输入的信号被积分和放大以检测数据，使用差分信号在高速下提供准确的数据检测，而不管过程的变化，电压电平， 或温度。
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公开(公告)号：US06812747B2
公开(公告)日：2004-11-02
申请号：US10420342
申请日：2003-04-22
IPC分类号： H03K522
CPC分类号： G11C16/30 , G05F3/262 , G11C5/143 , G11C5/147 , H03K17/302
摘要： A comparator compares a first voltage applied to a first input to a second voltage applied to a second input. The comparator delivers an output signal having a first value when the second voltage is higher than the first voltage, and having a second value when the second voltage is lower than the first voltage. The comparator includes first and second PMOS transistors arranged as current mirrors. The first PMOS transistor has its source connected to the first input of the comparator for receiving the first voltage. The second PMOS transistor has its source connected to the second input of the comparator for receiving the second voltage. The output of the comparator is connected to the drain of one of the transistors.
摘要翻译： 比较器将施加到第一输入的第一电压与施加到第二输入的第二电压进行比较。 当第二电压高于第一电压时，比较器输出具有第一值的输出信号，并且当第二电压低于第一电压时具有第二值。 比较器包括布置为电流镜的第一和第二PMOS晶体管。 第一PMOS晶体管的源极连接到比较器的第一输入以接收第一电压。 第二PMOS晶体管的源极连接到比较器的第二输入端，用于接收第二电压。 比较器的输出端连接到晶体管之一的漏极。
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公开(公告)号：US06693465B1
公开(公告)日：2004-02-17
申请号：US10345558
申请日：2003-01-16
IPC分类号： H03K522
CPC分类号： H03K5/2481 , H04L25/08
摘要： Circuitry is disclosed for detection of open inputs on an enhanced differential receiver. A pulldown terminator is coupled to the inputs of the enhanced differential receiver. If the differential inputs are not actively driven, the voltage on both differential inputs will be pulled to a predetermined voltage. When the voltage on the differential inputs reach a reference voltage, an active device detects that the reference voltage has been reached, and produces a predetermined logic value on an output of the enhanced differential receiver. The enhanced differential receiver is not subject to oscillation when not actively driven. Delay through the enhanced differential receiver is not substantially greater than delay through a conventional differential receiver consisting of only a differential amplifier.
摘要翻译： 公开了用于检测增强型差分接收器上的开放输入的电路。 下拉终端器耦合到增强型差分接收器的输入端。 如果差分输入未被主动驱动，则两个差分输入端的电压将被拉至预定的电压。 当差分输入上的电压达到参考电压时，有源器件检测到已经达到参考电压，并且在增强差分接收器的输出上产生预定的逻辑值。 增强型差分接收器不主动驱动时不会发生振荡。 通过增强型差分接收器的延迟通过仅由差分放大器组成的常规差分接收器的延迟实质上不大。
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公开(公告)号：US06680626B2
公开(公告)日：2004-01-20
申请号：US10161931
申请日：2002-06-05
申请人： Chit-Ah Mak , Bingda B. Wang , Eric West , Robert A. Olah
发明人： Chit-Ah Mak , Bingda B. Wang , Eric West , Robert A. Olah
IPC分类号： H03K522
CPC分类号： H03K5/2481
摘要： A differential receiver having a pair of cross-coupled signal conditioning devices improves transition time and data signal integrity. In an embodiment, the differential receiver includes two signal input nodes and a plurality of transistors, and two signal output nodes. The pair of cross-coupled signal conditioning devices are coupled to the transistors and function to reduce voltage swing between the two output nodes, thereby keeping the transistors in a saturation region.
摘要翻译： 具有一对交叉耦合信号调理装置的差分接收器改善了转换时间和数据信号完整性。 在一个实施例中，差分接收器包括两个信号输入节点和多个晶体管以及两个信号输出节点。 一对交叉耦合的信号调节装置耦合到晶体管并且用于减小两个输出节点之间的电压摆幅，从而将晶体管保持在饱和区域。
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公开(公告)号：US06664814B1
公开(公告)日：2003-12-16
申请号：US10199749
申请日：2002-07-18
IPC分类号： H03K522
CPC分类号： H03K19/018514 , H03K19/018585 , H04L25/0276 , H04L25/028
摘要： A circuit and method for driving the output signal, having a common-mode voltage and an output swing, of an integrated circuit. In accordance with an aspect of an embodiment of the present invention, a first power supply provides the termination voltage for the output signal and a second power supply provides the power to set the common mode voltage. In accordance with another aspect, the common-mode voltage and the output swing are programmable.
摘要翻译： 一种用于驱动具有集成电路的共模电压和输出摆幅的输出信号的电路和方法。 根据本发明的实施例的一个方面，第一电源为输出信号提供终止电压，第二电源提供设定共模电压的电力。 根据另一方面，共模电压和输出摆幅是可编程的。
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公开(公告)号：US06617887B2
公开(公告)日：2003-09-09
申请号：US10331223
申请日：2002-12-30
申请人： Michael A. Nix
发明人： Michael A. Nix
IPC分类号： H03K522
CPC分类号： H03K5/249 , H03F3/45753 , H03F3/45771 , H03K5/2481
摘要： A differential comparator having offset correction and common mode control for providing stable op amp output that changes only due to the original inputs coming into the comparator. The difference comparator has increased common-mode difference tolerance, and large op-amp offset tolerance, as well as fast decision time.
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公开(公告)号：US06591319B2
公开(公告)日：2003-07-08
申请号：US10284310
申请日：2002-10-31
申请人： Nasser A. Kurd , Robert J. Greiner
发明人： Nasser A. Kurd , Robert J. Greiner
IPC分类号： H03K522
CPC分类号： H03K5/1252 , G06F13/4077
摘要： In a processing system, a glitch protection circuit receives a strobe signal and a data receiver captures a data signal in response to an output from the glitch protection circuit. Several embodiments are disclosed. In a first embodiment, a glitch protection circuit generates an output that represents a logical multiplication of a strobe signal with a delayed version of itself. In another embodiment, a pair of glitch protection circuits each sense a strobe transition and become dormant until its partner senses a strobe transition. The pair operates in a toggling fashion.
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8.发明授权公开(公告)号：US06573760B1
公开(公告)日：2003-06-03
申请号：US09221263
申请日：1998-12-28
申请人： Thaddeus J. Gabara
发明人： Thaddeus J. Gabara
IPC分类号： H03K522
CPC分类号： H03K5/007 , H03F2203/45401 , H03K5/2481
摘要： A circuit for extracting a common mode data signal applied to a plurality of component signals. The circuit including a current driver, resistance, and a common mode extraction unit connected in series. The extraction unit has an impedance substantially proportional to the average voltage of the applied input signals and may be formed of a series of matched transistors connected in parallel. In a single-path configuration, when pairs of differential signals are applied, the voltage drop across the extraction unit is proportional to the overall common mode signal level carried by the differential signal components. In a multiple path configuration, two or more extraction units may be connected to a common current driver and configured in a differential amplifier configuration.
摘要翻译： 一种用于提取应用于多个分量信号的共模数据信号的电路。 该电路包括串联连接的电流驱动器，电阻和共模提取单元。 提取单元具有与施加的输入信号的平均电压成正比的阻抗，并且可以由并联连接的一系列匹配晶体管形成。 在单路配置中，当施加差分信号对时，提取单元两端的电压降与差分信号分量承载的总共模信号电平成比例。 在多路径配置中，两个或更多个提取单元可以连接到公共电流驱动器并且被配置在差分放大器配置中。
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公开(公告)号：US06559687B1
公开(公告)日：2003-05-06
申请号：US10047285
申请日：2002-01-14
申请人： Ken S. Hunt
发明人： Ken S. Hunt
IPC分类号： H03K522
CPC分类号： H03K5/2481
摘要： A full rail-to-rail CMOS comparator is provided. The comparator includes a gain stage and a bias stage. The bias stage is responsive to the common mode input voltage level to provide a bias signal that maintains the gain stage with an optimum operating range regardless of the level of the common mode input voltage, thus maintaining the comparator output responsive to the differential input voltage. Accordingly, when operating in the optimum operating range, duty cycle distortion of the signal at the comparator output is minimized. The comparator also offers improved performance due to a lower component count and fewer comparator stages, thus decreasing power consumption and improving propagation delays.
摘要翻译： 提供了完整的轨到轨CMOS比较器。 比较器包括增益级和偏置级。 偏置级响应于共模输入电压电平，以提供一个偏置信号，该偏置信号使得增益级保持最佳工作范围，而不管共模输入电压的电平如何，从而保持比较器输出响应差分输入电压。 因此，当在最佳工作范围内工作时，比较器输出处的信号的占空比失真被最小化。 比较器还提供了更高的性能，因为较低的元件数量和较少的比较器级，从而降低功耗并改善传播延迟。
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公开(公告)号：US06552580B2
公开(公告)日：2003-04-22
申请号：US09559498
申请日：2000-04-27
IPC分类号： H03K522
CPC分类号： G05F3/242
摘要： A multistage analog circuit for independently controlling a bias current in each stage of the multistage analog circuit having an input stage, an intermediate stage, and an output stage, includes a first current source which controls the input stage of the circuit, a second current source which controls the intermediate stage of the circuit, and a third current source which controls the output stage of the circuit. The bias current in each stage of the circuit is set by the first, second, and third current sources. An output voltage of the circuit is capable of remaining the same when the first current source is changed to affect an input transconductance of the circuit.
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