公开(公告)号：US09064717B2

公开(公告)日：2015-06-23

申请号：US12615175

申请日：2009-11-09

Applicant: Sampath Purushothaman ,  Mary E. Rothwell ,  Ghavam Ghavami Shahidi ,  Roy Rongqing Yu

Inventor： Sampath Purushothaman ,  Mary E. Rothwell ,  Ghavam Ghavami Shahidi ,  Roy Rongqing Yu

IPC: H01L21/50 ,  H01L25/065 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L25/50 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593

Abstract: A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.

Abstract translation: 三维器件堆叠结构包括两个或更多个有源器件和互连层，其通过衬底通孔进一步连接在一起。 形成三维器件堆叠结构的方法包括对准，通过层压粘接，变薄和后变薄处理。 通孔特征使得能够通过层压工艺和任何后续工艺步骤保持对准，从而与现有技术相比实现机械上更坚固的堆叠结构。

公开(公告)号：US08968583B2

公开(公告)日：2015-03-03

申请号：US11782996

申请日：2007-07-25

Applicant: Mary Beth Rothwell ,  Roy Rongqing Yu

Inventor： Mary Beth Rothwell ,  Roy Rongqing Yu

IPC: H01L21/4763 ,  H01L21/302 ,  H01L21/461 ,  H01B13/00 ,  B44C1/22 ,  B23P15/00 ,  C03C25/00 ,  C23F1/00 ,  C03C15/00 ,  C03C25/68 ,  C25F3/00 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/02074

Abstract: A method for cleaning a dielectric and metal structure within a microelectronic structure uses an oxygen containing plasma treatment, followed by an alcohol treatment, in turn followed by an aqueous organic acid treatment. Another method for cleaning a dielectric and metal structure within a microelectronic structure uses an aqueous surfactant treatment followed by an alcohol treatment and finally followed by an aqueous organic acid treatment. The former method may be used to clean a plasma etch residue from a dual damascene aperture. The second method may be used to clean a chemical mechanical polish planarizing residue from a dual damascene structure. The two methods may be used sequentially, absent any intervening or subsequent sputtering method, to provide a dual damascene structure within a microelectronic structure.

Abstract translation: 用于清洁微电子结构内的电介质和金属结构的方法使用含氧等离子体处理，随后进行醇处理，随后进行含水有机酸处理。 用于清洁微电子结构内的电介质和金属结构的另一种方法使用水性表面活性剂处理，然后进行醇处理，最后进行含水有机酸处理。 前一种方法可用于从双镶嵌孔眼清洗等离子体蚀刻残留物。 第二种方法可用于从双镶嵌结构清洁化学机械抛光平面化残留物。 两种方法可以顺序地使用，没有任何中间或随后的溅射方法，以在微电子结构内提供双镶嵌结构。

公开(公告)号：US07994639B2

公开(公告)日：2011-08-09

申请号：US11831138

申请日：2007-07-31

Applicant: James J. Bucchignano ,  Gerald Warren Gibson, Jr. ,  Mary Beth Rothwell ,  Roy Rongqing Yu

Inventor： James J. Bucchignano ,  Gerald Warren Gibson, Jr. ,  Mary Beth Rothwell ,  Roy Rongqing Yu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/4763

CPC classification number: H01L21/76808 ,  G03F9/7076

Abstract: A microelectronic structure, and in particular a semiconductor structure, includes a substrate and a dielectric layer located over the substrate. In addition at least one alignment mark is located interposed between the dielectric layer and the substrate. The at least one alignment mark comprises, or preferably consists essentially of, at least one substantially present element having an atomic number at least 5 greater than a highest atomic number substantially present element within materials surrounding the alignment mark Also included within the microelectronic structure is a dual damascene aperture located within the dielectric layer. The dual damascene aperture may be fabricated using, among other methods, a hybrid lithography method that uses direct write lithography and optical lithography, in conjunction with the at least one alignment mark and an electron beam as an alignment beam.

Abstract translation: 微电子结构，特别是半导体结构，包括位于衬底上方的衬底和电介质层。 此外，至少一个对准标记位于介电层和衬底之间。 所述至少一个对准标记包含或优选地基本上由至少一个基本上呈现的元素，所述元素的原子序数比围绕对准标记的材料内的最高原子序数基本上呈现的元素至少大5。还包括在微电子结构内的是 位于电介质层内的双镶嵌孔。 双镶嵌孔可以使用除了其他方法之一的混合光刻方法制造，所述混合光刻方法使用直接写光刻和光学光刻，结合至少一个对准标记和电子束作为对准光束。

公开(公告)号：US07855455B2

公开(公告)日：2010-12-21

申请号：US12239688

申请日：2008-09-26

Applicant: Sampath Purushothaman ,  Mary E. Rothwell ,  Ghavam Ghavami Shahidi ,  Roy Rongqing Yu

Inventor： Sampath Purushothaman ,  Mary E. Rothwell ,  Ghavam Ghavami Shahidi ,  Roy Rongqing Yu

IPC: H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L23/481 ,  H01L24/11 ,  H01L24/83 ,  H01L24/90 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2221/68377 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/05184 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/1147 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/83121 ,  H01L2224/83141 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/00014

Abstract: A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.

Abstract translation: 三维器件堆叠结构包括两个或更多个有源器件和互连层，其通过衬底通孔进一步连接在一起。 形成三维器件堆叠结构的方法包括对准，通过层压粘接，变薄和后变薄处理。 通孔特征使得能够通过层压工艺和任何后续工艺步骤保持对准，从而与现有技术相比实现机械上更坚固的堆叠结构。

公开(公告)号：US20090032978A1

公开(公告)日：2009-02-05

申请号：US11831138

申请日：2007-07-31

Applicant: James J. Bucchignano ,  Gerald Warren Gibson, JR. ,  Mary Beth Rothwell ,  Roy Rongqing Yu

Inventor： James J. Bucchignano ,  Gerald Warren Gibson, JR. ,  Mary Beth Rothwell ,  Roy Rongqing Yu

IPC: H01L23/544 ,  H01L21/4763

CPC classification number: H01L21/76808 ,  G03F9/7076

Abstract: A microelectronic structure, and in particular a semiconductor structure, includes a substrate and a dielectric layer located over the substrate. In addition at least one alignment mark is located interposed between the dielectric layer and the substrate. The at least one alignment mark comprises, or preferably consists essentially of, at least one substantially present element having an atomic number at least 5 greater than a highest atomic number substantially present element within materials surrounding the alignment mark Also included within the microelectronic structure is a dual damascene aperture located within the dielectric layer. The dual damascene aperture may be fabricated using, among other methods, a hybrid lithography method that uses direct write lithography and optical lithography, in conjunction with the at least one alignment mark and an electron beam as an alignment beam.

Abstract translation: 微电子结构，特别是半导体结构，包括位于衬底上方的衬底和电介质层。 此外，至少一个对准标记位于介电层和衬底之间。 所述至少一个对准标记包含或优选地基本上由至少一个基本上呈现的元素，所述元素的原子序数比围绕对准标记的材料内的最高原子序数基本上呈现的元素至少大5。还包括在微电子结构内的是 位于电介质层内的双镶嵌孔。 双镶嵌孔可以使用除了其他方法之一的混合光刻方法制造，所述混合光刻方法使用直接写光刻和光学光刻，结合至少一个对准标记和电子束作为对准光束。

公开(公告)号：US20100078770A1

公开(公告)日：2010-04-01

申请号：US12239688

申请日：2008-09-26

Applicant: Sampath Purushothaman ,  Mary E. Rothwell ,  Ghavam Ghavami Shahidi ,  Roy Rongqing Yu

Inventor： Sampath Purushothaman ,  Mary E. Rothwell ,  Ghavam Ghavami Shahidi ,  Roy Rongqing Yu

IPC: H01L23/52 ,  H01L21/60

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L23/481 ,  H01L24/11 ,  H01L24/83 ,  H01L24/90 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2221/68377 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/05184 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/1147 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/83121 ,  H01L2224/83141 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/00014

Abstract: A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.

Abstract translation: 三维器件堆叠结构包括两个或更多个有源器件和互连层，其通过衬底通孔进一步连接在一起。 形成三维器件堆叠结构的方法包括对准，通过层压粘接，变薄和后变薄处理。 通孔特征使得能够通过层压工艺和任何后续工艺步骤保持对准，从而与现有技术相比实现机械上更坚固的堆叠结构。

公开(公告)号：US07084479B2

公开(公告)日：2006-08-01

申请号：US10731377

申请日：2003-12-08

Applicant: Shyng-Tsong Chen ,  Stefanie Ruth Chiras ,  Matthew Earl Colburn ,  Timothy Joseph Dalton ,  Jeffrey Curtis Hedrick ,  Elbert Emin Huang ,  Kaushik Arun Kumar ,  Michael Wayne Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Robert Rosenburg ,  Christy Sensenich Tyberg ,  Roy RongQing Yu

Inventor： Shyng-Tsong Chen ,  Stefanie Ruth Chiras ,  Matthew Earl Colburn ,  Timothy Joseph Dalton ,  Jeffrey Curtis Hedrick ,  Elbert Emin Huang ,  Kaushik Arun Kumar ,  Michael Wayne Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Robert Rosenburg ,  Christy Sensenich Tyberg ,  Roy RongQing Yu

IPC: H01L29/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

公开(公告)号：US20120193752A1

公开(公告)日：2012-08-02

申请号：US13016994

申请日：2011-01-29

Applicant: Sampath Purushothaman ,  Roy Rongqing Yu

Inventor： Sampath Purushothaman ,  Roy Rongqing Yu

IPC: H01L27/12 ,  H01L21/60

CPC classification number: H01L21/76897 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/76251 ,  H01L21/76256 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/544 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/89 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649 ,  H01L2221/68372 ,  H01L2223/54426 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/11002 ,  H01L2224/1148 ,  H01L2224/11616 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/8013 ,  H01L2224/81005 ,  H01L2224/81065 ,  H01L2224/81075 ,  H01L2224/8109 ,  H01L2224/81093 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81209 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

Abstract translation: 通过这种方法制造的工艺和最终的制品包括将包含硅绝缘体（SOI）的顶部硅晶片中的将底部硅晶片中的底部器件层连接到顶部器件层中的底部器件层所需的通孔形成， 晶圆。 通孔以这样的方式设置，使得它们从顶部晶片的线（MOL）互连的中间延伸到SOI晶片的掩埋氧化物（BOX）层，其中提供了适当的绝缘以将它们与SOI器件层隔离开。

公开(公告)号：US20100200992A1

公开(公告)日：2010-08-12

申请号：US12763596

申请日：2010-04-20

Applicant: Sampath Purushothaman ,  Mary E. Rothwell ,  Ghavam Ghavami Shahidi ,  Roy Rongqing Yu

Inventor： Sampath Purushothaman ,  Mary E. Rothwell ,  Ghavam Ghavami Shahidi ,  Roy Rongqing Yu

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L24/83 ,  H01L24/90 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/105 ,  H01L2221/68377 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/83121 ,  H01L2224/83141 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/01028

Abstract: A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.

Abstract translation: 三维器件堆叠结构包括两个或更多个有源器件和互连层，其通过衬底通孔进一步连接在一起。 形成三维器件堆叠结构的方法包括对准，通过层压粘接，变薄和后变薄处理。 通孔特征使得能够通过层压工艺和任何后续工艺步骤保持对准，从而与现有技术相比实现机械上更坚固的堆叠结构。

公开(公告)号：US20090029543A1

公开(公告)日：2009-01-29

申请号：US11782996

申请日：2007-07-25

Applicant: Mary Beth Rothwell ,  Roy Rongqing Yu

Inventor： Mary Beth Rothwell ,  Roy Rongqing Yu

IPC: H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/02074

Abstract: A method for cleaning a dielectric and metal structure within a microelectronic structure uses an oxygen containing plasma treatment, followed by an alcohol treatment, in turn followed by an aqueous organic acid treatment. Another method for cleaning a dielectric and metal structure within a microelectronic structure uses an aqueous surfactant treatment followed by an alcohol treatment and finally followed by an aqueous organic acid treatment. The former method may be used to clean a plasma etch residue from a dual damascene aperture. The second method may be used to clean a chemical mechanical polish planarizing residue from a dual damascene structure. The two methods may be used sequentially, absent any intervening or subsequent sputtering method, to provide a dual damascene structure within a microelectronic structure.

Abstract translation: 用于清洁微电子结构内的电介质和金属结构的方法使用含氧等离子体处理，随后进行醇处理，随后进行含水有机酸处理。 用于清洁微电子结构内的电介质和金属结构的另一种方法使用水性表面活性剂处理，然后进行醇处理，最后进行含水有机酸处理。 前一种方法可用于从双镶嵌孔眼清洗等离子体蚀刻残留物。 第二种方法可用于从双镶嵌结构清洁化学机械抛光平面化残留物。 两种方法可以顺序地使用，没有任何中间或随后的溅射方法，以在微电子结构内提供双镶嵌结构。