公开(公告)号：US08753460B2

公开(公告)日：2014-06-17

申请号：US13015638

申请日：2011-01-28

Applicant: Sarah H. Knickerbocker ,  Jonathan H. Griffith

Inventor： Sarah H. Knickerbocker ,  Jonathan H. Griffith

IPC: B32B37/02

CPC classification number: H01L21/6835 ,  H01L2221/68327

Abstract: Methods and systems for reinforcing the periphery of a semiconductor wafer bonded to a carrier are disclosed. In one embodiment, additional adhesive is applied to the semiconductor wafer prior to bonding. The additional adhesive seeps into a crevice between the carrier and wafer and provides reinforcement. In another embodiment, adhesive is applied to the crevice by a dispenser after the wafer is bonded to the glass carrier.

Abstract translation: 公开了用于加强结合到载体的半导体晶片的周边的方法和系统。 在一个实施例中，在粘合之前将另外的粘合剂施加到半导体晶片。 附加的粘合剂渗入载体和晶片之间的缝隙并提供增强。 在另一个实施例中，在将晶片结合到玻璃载体上之后，通过分配器将粘合剂施加到缝隙。

公开(公告)号：US08314500B2

公开(公告)日：2012-11-20

申请号：US11616919

申请日：2006-12-28

Applicant: Luc Belanger ,  Stephen L. Buchwalter ,  Leena Paivikki Buchwalter ,  Ajay P. Giri ,  Jonathan H. Griffith ,  Donald W. Henderson ,  Sung Kwon Kang ,  Eric H. Laine ,  Christian Lavoie ,  Paul A. Lauro ,  Valérie Anne Oberson ,  Da-Yuan Shih ,  Kamalesh K Srivastava ,  Michael J. Sullivan

Inventor： Luc Belanger ,  Stephen L. Buchwalter ,  Leena Paivikki Buchwalter ,  Ajay P. Giri ,  Jonathan H. Griffith ,  Donald W. Henderson ,  Sung Kwon Kang ,  Eric H. Laine ,  Christian Lavoie ,  Paul A. Lauro ,  Valérie Anne Oberson ,  Da-Yuan Shih ,  Kamalesh K Srivastava ,  Michael J. Sullivan

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/12 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/114 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2224/13099

Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

Abstract translation: 一种适于将微电子器件芯片倒装连接到封装的互连结构，包括二层，三层或四层限流冶金，包括粘附/反应阻挡层，并且具有与含锡的组分反应的焊料可湿性层 无铅焊料，使得可焊接层在焊接期间可以完全消耗，但在焊接期间与无铅焊料接触后，阻挡层保持不变。 一个或多个无铅焊料球选择性地位于焊料润湿层上，该无铅焊球包含锡作为主要成分和一种或多种合金成分。

公开(公告)号：US4588471A

公开(公告)日：1986-05-13

申请号：US715253

申请日：1985-03-25

Applicant: Jonathan H. Griffith ,  Everton H. Henriques ,  James L. Kehoe, III ,  Marshall J. Suskie

Inventor： Jonathan H. Griffith ,  Everton H. Henriques ,  James L. Kehoe, III ,  Marshall J. Suskie

IPC: C23F1/26 ,  H05K3/06 ,  H05K3/24 ,  H05K3/38 ,  C23F1/02

CPC classification number: C03C17/40 ,  C23F1/26 ,  C03C2218/33 ,  H05K3/067 ,  H05K3/244 ,  H05K3/388

Abstract: Chrome/copper/chrome conductor arrays deposited on glass plates are etched with an aqueous acidic composition which contains an acid and a thiourea compound.

Abstract translation: 用含有酸和硫脲化合物的酸性组合物蚀刻沉积在玻璃板上的铬/铜/铬导体阵列。

公开(公告)号：US07572726B2

公开(公告)日：2009-08-11

申请号：US11271760

申请日：2005-11-10

Applicant: Julie C. Biggs ,  Tien-Jen Cheng ,  David E. Eichstadt ,  Lisa A. Fanti ,  Jonathan H. Griffith ,  Randolph F. Knarr ,  Sarah H. Knickerbocker ,  Kevin S. Petrarca ,  Roger A. Quon ,  Wolfgang Sauter ,  Kamalesh K. Srivastava ,  Richard P. Volant

Inventor： Julie C. Biggs ,  Tien-Jen Cheng ,  David E. Eichstadt ,  Lisa A. Fanti ,  Jonathan H. Griffith ,  Randolph F. Knarr ,  Sarah H. Knickerbocker ,  Kevin S. Petrarca ,  Roger A. Quon ,  Wolfgang Sauter ,  Kamalesh K. Srivastava ,  Richard P. Volant

IPC: H01L21/44

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

Abstract translation: 一种在（I / C）芯片中形成引线键合的方法，包括：提供具有导电焊盘的I / C芯片，所述导电焊盘与覆盖所述焊盘的至少一层电介质材料进行引线接合; 通过暴露所述垫的一部分的电介质材料形成开口。 在衬垫的暴露表面和开口表面上形成至少第一导电层。 在第一导电层上形成种子层; 在种子层上施加光致抗蚀剂; 曝光和显影光致抗蚀剂，其显露出围绕开口的种子层的表面; 去除暴露的种子层; 去除开口中的光致抗蚀剂材料，露出种子层。 在开口中的种子层上电镀至少一层第二导电材料层，以及去除围绕开口的电介质层上的第一导电层。 本发明还包括所得到的结构。

公开(公告)号：US06293457B1

公开(公告)日：2001-09-25

申请号：US09590119

申请日：2000-06-08

Applicant: Kamalesh K. Srivastava ,  Jonathan H. Griffith ,  Mary C. Cullinan-Scholl ,  William H. Brearley ,  Peter C. Wade

Inventor： Kamalesh K. Srivastava ,  Jonathan H. Griffith ,  Mary C. Cullinan-Scholl ,  William H. Brearley ,  Peter C. Wade

IPC: B23K3102

CPC classification number: H01L24/05 ,  C23F1/26 ,  H01L21/76804 ,  H01L24/03 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05082 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/3011 ,  H01L2924/00014

Abstract: Form a solder connector on a semiconductor device starting with a first step of forming at least one dielectric layer over a doped semiconductor substrate. Then form a hole through the dielectric layer down to the semiconductor substrate. Form a metal conductor in the hole. Form intermediate layers over the metal conductor and the dielectric layer. Then form a tapered opening down to the surface of the metal conductor. Form BLM layers including a titanium-tungsten (TiW) layer over the metal conductor and the dielectric layer with the remainder of the BLM layers being formed over the TiW layer. Form a mask over the top surface of the BLM layers with a patterning through hole located above the metal conductor exposing a portion of the surface of the BLM layers. Plate a C4 solder bump on the BLM layers in the patterning hole. Remove the mask. Wet etch away the BLM layers aside from the solder bump leaving a residual TiW layer over the dielectric layer. Perform a dry etching process to remove the residual TiW layer aside from the solder bump. Then, end the dry etching when the end point has been reached. Finally, heat the solder bump in a reflow process to form a C4 solder ball.

Abstract translation: 在半导体器件上形成焊料连接器，从在掺杂半导体衬底上形成至少一个电介质层的第一步骤开始。 然后通过介电层形成一个穿过半导体衬底的孔。 在孔中形成金属导体。 在金属导体和电介质层上形成中间层。 然后形成锥形开口，直到金属导体的表面。 在金属导体上形成包括钛 - 钨（TiW）层的BLM层，其中剩余的BLM层形成在TiW层上。 在BLM层的顶表面上形成掩模，其中图案化通孔位于金属导体上方，露出BLM层表面的一部分。 在图案化孔中的BLM层上贴上C4焊料凸块。 取下面具。 湿式蚀刻除了焊料凸块之外的BLM层，在电介质层上留下残留的TiW层。 执行干蚀刻工艺以除去焊料凸块之外的残余TiW层。 然后，当达到终点时结束干蚀刻。 最后，在回流焊过程中加热焊料凸块以形成C4焊球。

公开(公告)号：US06228665B1

公开(公告)日：2001-05-08

申请号：US09597637

申请日：2000-06-20

Applicant: Jonathan H. Griffith ,  Ronald L. Smith ,  Roger L. Verkuil

Inventor： Jonathan H. Griffith ,  Ronald L. Smith ,  Roger L. Verkuil

IPC: G01R3126

CPC classification number: H01L22/12

Abstract: A measurement of thickness of a metal oxide layer on a solder ball connection during semiconductor fabrication is demonstrated by an in-situ capacitance measurement of the oxide layer. A linear relationship is shown between the reactance of the metal oxide and its thickness. This linearity is derived empirically, and correlated to Auger Spectroscopy test results for accuracy. The linear relationship demonstrated with these measurements exhibits a linear correlation coefficient, R2, greater than or equal to 0.974. This close, linear relationship allows for accurate testing of the oxide thickness using standard electrical parameter measurements during wafer fabrication. The method requires the determination of an analytical relationship between dielectric thickness and dielectric capacitance; the performance of an in-situ test of the dielectric layer capacitance including measuring the dielectric layer capacitance; and, the calculation of the dielectric layer thickness by using reactance values, calculated from the measured dielectric layer capacitance, as a variable within the analytical relationship.

Abstract translation: 通过氧化物层的原位电容测量来证明在半导体制造期间焊球连接上的金属氧化物层的厚度的测量。 金属氧化物的电抗与其厚度之间呈线性关系。 这种线性是经验派生的，并与俄歇光谱测试结果相关，以获得准确性。 用这些测量证明的线性关系表现出线性相关系数R2，大于或等于0.974。 这种密切的线性关系允许在晶片制造期间使用标准电参数测量来精确测量氧化物厚度。该方法需要确定介电厚度和介电电容之间的分析关系; 介质层电容的原位测试的性能包括测量介电层电容; 并且通过使用由测量的介电层电容计算的电抗值作为分析关系中的变量来计算电介质层厚度。

公开(公告)号：US20120193014A1

公开(公告)日：2012-08-02

申请号：US13015638

申请日：2011-01-28

Applicant: SARAH H. KNICKERBOCKER ,  Jonathan H. Griffith

Inventor： SARAH H. KNICKERBOCKER ,  Jonathan H. Griffith

IPC: B32B37/12 ,  B32B37/06 ,  B32B38/10 ,  B32B37/10 ,  B32B37/14 ,  B32B38/00 ,  B32B37/02 ,  B32B37/08

CPC classification number: H01L21/6835 ,  H01L2221/68327

Abstract: Methods and systems for reinforcing the periphery of a semiconductor wafer bonded to a carrier are disclosed. In one embodiment, additional adhesive is applied to the semiconductor wafer prior to bonding. The additional adhesive seeps into a crevice between the carrier and wafer and provides reinforcement. In another embodiment, adhesive is applied to the crevice by a dispenser after the wafer is bonded to the glass carrier.

Abstract translation: 公开了用于加强结合到载体的半导体晶片的周边的方法和系统。 在一个实施例中，在粘合之前将另外的粘合剂施加到半导体晶片。 附加的粘合剂渗入载体和晶片之间的缝隙并提供增强。 在另一个实施例中，在将晶片结合到玻璃载体上之后，通过分配器将粘合剂施加到缝隙。

公开(公告)号：US07767575B2

公开(公告)日：2010-08-03

申请号：US12348143

申请日：2009-01-02

Applicant: Kamalesh K. Srivastava ,  Subhash L. Shinde ,  Tien-Jen Cheng ,  Sarah H. Knickerbocker ,  Roger A. Quinn ,  William E. Sablinski ,  Julie C. Biggs ,  David E. Eichstadt ,  Jonathan H. Griffith

Inventor： Kamalesh K. Srivastava ,  Subhash L. Shinde ,  Tien-Jen Cheng ,  Sarah H. Knickerbocker ,  Roger A. Quinn ,  William E. Sablinski ,  Julie C. Biggs ,  David E. Eichstadt ,  Jonathan H. Griffith

IPC: H01L21/44 ,  H01L23/48

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/351 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/13 ,  H01L2924/00014

Abstract: A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter.

Abstract translation: 用于形成半导体器件的互连结构的方法包括在钝化层中限定通孔，以暴露半导体器件中的顶部金属层。 在钝化层，通孔的侧壁和顶部金属层上形成种子层。 阻挡层形成在种子层的暴露部分上，由第一直径的第一图案化开口限定的暴露部分和使用第二直径的第二图案化开口在阻挡层上形成焊料材料。 第二图案化开口被配置为使得第二直径大于第一直径。

公开(公告)号：US20080157395A1

公开(公告)日：2008-07-03

申请号：US11616919

申请日：2006-12-28

Applicant: Luc Belanger ,  Stephen L. Buchwalter ,  Leena Paivikki Buchwalter ,  Ajay P. Giri ,  Jonathan H. Griffith ,  Donald W. Henderson ,  Sung Kwon Kang ,  Eric H. Laine ,  Christian Lavoie ,  Paul A. Lauro ,  Valerie Anne Oberson ,  Da-Yuan Shih ,  Kamalesh K. Srivastava ,  Michael J. Sullivan

Inventor： Luc Belanger ,  Stephen L. Buchwalter ,  Leena Paivikki Buchwalter ,  Ajay P. Giri ,  Jonathan H. Griffith ,  Donald W. Henderson ,  Sung Kwon Kang ,  Eric H. Laine ,  Christian Lavoie ,  Paul A. Lauro ,  Valerie Anne Oberson ,  Da-Yuan Shih ,  Kamalesh K. Srivastava ,  Michael J. Sullivan

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/12 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/114 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2224/13099

Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

Abstract translation: 一种适于将微电子器件芯片倒装连接到封装的互连结构，包括二层，三层或四层限流冶金，包括粘附/反应阻挡层，并且具有与含锡的组分反应的焊料可湿性层 无铅焊料，使得可焊接层在焊接期间可以完全消耗，但在焊接期间与无铅焊料接触后，阻挡层保持不变。 一个或多个无铅焊料球选择性地位于焊料润湿层上，该无铅焊球包含锡作为主要成分和一种或多种合金成分。

公开(公告)号：US07144490B2

公开(公告)日：2006-12-05

申请号：US10707047

申请日：2003-11-18

Applicant: Tien-Jen Cheng ,  David E. Eichstadt ,  Jonathan H. Griffith ,  Sarah H. Knickerbocker ,  Rosemary A. Previti-Kelly ,  Roger A. Quon ,  Kamalesh K. Srivastava ,  Keith Kwong-Hon Wong

Inventor： Tien-Jen Cheng ,  David E. Eichstadt ,  Jonathan H. Griffith ,  Sarah H. Knickerbocker ,  Rosemary A. Previti-Kelly ,  Roger A. Quon ,  Kamalesh K. Srivastava ,  Keith Kwong-Hon Wong

IPC: C25D5/02 ,  C25D7/12

CPC classification number: H01L24/13 ,  C25D5/022 ,  C25D5/12 ,  C25D7/123 ,  H01L24/11 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05644 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2224/29099 ,  H01L2224/05552 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A method for selective electroplating of a semiconductor input/output (I/O) pad includes forming a titanium-tungsten (TiW) layer over a passivation layer on a semiconductor substrate, the TiW layer further extending into an opening formed in the passivation layer for exposing the I/O pad, such that the TiW layer covers sidewalls of the opening and a top surface of the I/O pad. A seed layer is formed over the TiW layer, and portions of the seed layer are selectively removed such that remaining seed layer material corresponds to a desired location of interconnect metallurgy for the I/O pad. At least one metal layer is electroplated over the remaining seed layer material, using the TiW layer as a conductive electroplating medium.

Abstract translation: 一种用于半导体输入/输出（I / O）焊盘的选择性电镀的方法包括在半导体衬底上的钝化层上形成钛 - 钨（TiW）层，所述TiW层进一步延伸到形成在钝化层中的开口中 暴露I / O焊盘，使得TiW层覆盖开口的侧壁和I / O焊盘的顶表面。 在TiW层上形成种子层，并且选择性地去除种子层的部分，使得剩余的种子层材料对应于用于I / O焊盘的互连冶金的期望位置。 使用TiW层作为导电电镀介质，在剩余的种子层材料上电镀至少一层金属层。