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    Planar DC-DC converter for multi-volt electrical applications
    1.
    发明申请
    Planar DC-DC converter for multi-volt electrical applications 审中-公开
    用于多伏电气应用的平面DC-DC转换器

    公开(公告)号：US20040056534A1

    公开(公告)日：2004-03-25

    申请号：US10454260

    申请日：2003-06-03

    Applicant: International Rectifier Corp.

    Inventor： Mario Linke ,  Marc Bleukx

    IPC: H02J001/00

    CPC classification number: H02J1/08 ,  B60R16/03 ,  F02D41/3005 ,  F02D2400/14 ,  F02D2400/16 ,  H02J2001/008 ,  Y10T307/675

    Abstract: An electrical arrangement provides power to a plurality of electrical systems, the electrical arrangement including a plurality of voltage buses; a plurality of voltage sources configured to supply respective electrical voltage potentials, the voltage sources being respectively assigned to the voltage buses, the voltage sources supplying the respective electrical voltage potentials to the respective voltage buses; at least one electrical system assigned to and electrically coupled to each of the voltage buses to receive electrical power; and a DC-DC converter arrangement electrically coupled to the voltage buses, the DC-DC converter being configured to convert at least one of the respective voltage potentials to another one of the respective voltage potentials, the DC-DC converter being mechanically and proximally coupled to at least one of the voltage sources.

    Abstract translation: 电气布置为多个电气系统提供电力，电气装置包括多个电压总线; 多个电压源，被配置为提供相应的电压电位，所述电压源分别被分配给所述电压总线，所述电压源将各个电压电位提供给各个电压总线; 至少一个电气系统被分配并电耦合到每个电压总线以接收电力; 以及电耦合到所述电压总线的DC-DC转换器布置，所述DC-DC转换器被配置为将各个电压电位中的至少一个转换为相应电压电位中的另一个，所述DC-DC转换器机械地和近端耦合 至少一个电压源。

    Rad Hard MOSFET with graded body diode junction and reduced on resistance
    2.
    发明申请
    Rad Hard MOSFET with graded body diode junction and reduced on resistance 有权
    Rad Hard MOSFET具有分级体二极管结和降低导通电阻

    公开(公告)号：US20030205829A1

    公开(公告)日：2003-11-06

    申请号：US10138164

    申请日：2002-05-01

    Applicant: International Rectifier Corp.

    Inventor： Milton J. Boden JR.

    IPC: H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/113 ,  H01L031/119

    CPC classification number: H01L29/7802 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095

    Abstract: A Rad Hard MOSFET has a plurality of closely spaced base strips which have respective source to form invertible surface channels with the opposite sides of each of the stripes. A non-DMOS late gate oxide and overlying conductive polysilicon gate are formed after the source and base regions have been diffused. The base strips are spaced by about 0.6 microns, and the polysilicon gate stripes are about 3.2 microns wide. An enhancement region is implanted through spaced narrow window early in the process and are located in the JFET common conduction region which is later formed by and between the spaced base stripes. The device is a high voltage (greater than 25 volts) device with very low gate capacitance and very low on resistance. An early and deep (1.6 micron) P channel implant and diffusion are formed before the main channel is formed to produce a graded body diode junction.

    Abstract translation: Rad硬MOSFET具有多个紧密间隔的基带，其具有相应的源以与每个条的相对侧形成可逆表面通道。 在源极和基极区域扩散之后形成非DMOS后栅极氧化物和上覆导电多晶硅栅极。 基带间隔约0.6微米，多晶硅栅极条宽约3.2微米。 增强区域在该过程的早期通过间隔窄的窗口注入并且位于JFET共同导电区域中，后者由隔开的基底条纹之间和之间形成。 该器件是具有非常低栅极电容和非常低导通电阻的高电压（大于25伏特）器件。 在形成主通道之前形成早期和深（1.6微米）的P沟道注入和扩散以产生分级体二极管结。

    Mosfet with reduced threshold voltage and on resistance and process for its manufacture
    4.
    发明申请
    Mosfet with reduced threshold voltage and on resistance and process for its manufacture 有权
    Mosfet具有降低的阈值电压和电阻及其制造工艺

    公开(公告)号：US20030089945A1

    公开(公告)日：2003-05-15

    申请号：US10044427

    申请日：2001-11-09

    Applicant: International Rectifier Corp.

    Inventor： Thomas Herman ,  Harold Davis ,  Kyle Spring ,  Jianjun Cao

    IPC: H01L031/113

    CPC classification number: H01L29/7802 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/41766

    Abstract: A vertical conduction MOSFET having a reduced on resistance RDSON as well as reduced threshold voltage Vth, and an improved resistance to punchthrough and walkout has an extremely shallow source diffusion, of less than 0.3 microns in depth and an extremely shallow channel diffusion, of less than about 3 microns in depth. In a P channel version, phosphorus is implanted into the bottom of a contact trench and into the channel region with an implant energy of 400 keV for a singly charged phosphorus ion or 200 keV for a doubly charged ion, thereby to prevent walkout of the threshold voltage.

    Abstract translation: 具有降低的导通电阻RDSON和降低的阈值电压Vth的垂直导通MOSFET以及改进的穿通和迂回阻力具有小于0.3微米深度的极浅源极扩散和小于0.3微米的通道扩散。 约3微米深。 在P沟道版本中，磷被注入到接触沟槽的底部并且注入到沟道区域中，对于单电荷的磷离子或200keV的注入能量为400keV，用于双电荷离子，从而防止阈值 电压。

    Trench fet with self aligned source and contact
    5.
    发明申请
    Trench fet with self aligned source and contact 有权
    具有自对准源和接触的沟槽胎

    公开(公告)号：US20030085422A1

    公开(公告)日：2003-05-08

    申请号：US10234303

    申请日：2002-08-30

    Applicant: International Rectifier Corp.

    Inventor： Adam I. Amali ,  Naresh Thapar

    IPC: H01L021/336 ,  H01L029/76 ,  H01L031/062

    CPC classification number: H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66734 ,  H01L29/7811

    Abstract: A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with the top of the silicon. Source regions of short lateral extent extend into the trench walls to a depth below the top of the polysilicon. A trench termination is formed having an insulation oxide liner covered by a polysilicon layer, covered in turn by a deposited oxide.

    Abstract translation: 沟槽型功率MOS器件具有衬有氧化物并填充有导电多晶硅的多个隔开的沟槽。 多晶硅填料的顶部位于顶部硅表面之下，并用沉积的氧化物封盖，其顶部与硅的顶部齐平。 短横向范围的源区域延伸到沟槽壁中至多晶硅顶部的深度。 形成具有由多晶硅层覆盖的绝缘氧化物衬垫的沟槽端接，并且依次由被沉积的氧化物覆盖。

    Process for counter doping N-type silicon in Schottky device with Ti silicide barrier
    6.
    发明申请
    Process for counter doping N-type silicon in Schottky device with Ti silicide barrier 有权
    在具有Ti硅化物屏障的肖特基器件中反向掺杂N型硅的工艺

    公开(公告)号：US20030062585A1

    公开(公告)日：2003-04-03

    申请号：US10254112

    申请日：2002-09-25

    Applicant: International Rectifier Corp.

    Inventor： Kohji Andoh ,  Davide Chiola ,  Daniel M. Kinzer

    IPC: H01L027/095

    CPC classification number: H01L27/0814 ,  H01L29/66143 ,  H01L29/8725

    Abstract: A Schottky diode has a barrier height which is adjusted by boron implant through a titanium silicide Schottky contact and into the underlying Nnull silicon substrate which receives the titanium silicide contact. The implant is a low energy, of about 10 keV (non critical) and a low dose of less than about 1E12 atoms per cm2 (non-critical).

    Abstract translation: 肖特基二极管具有通过硼注入通过硅化钛肖特基接触并进入接收硅化钛接触的下面的N-硅衬底中的势垒高度。 植入物是约10keV（非临界）和小于约1E12原子/ cm 2（非关键）的低能量的低能量。

    Termination structure for superjunction device
    7.
    发明申请
    Termination structure for superjunction device 有权
    超级连接装置的端接结构

    公开(公告)号：US20030011046A1

    公开(公告)日：2003-01-16

    申请号：US10190152

    申请日：2002-07-03

    Applicant: International Rectifier Corp.

    Inventor： Zhijun Qu

    IPC: H01L029/93

    CPC classification number: H01L29/7811 ,  H01L29/0634 ,  H01L29/41766 ,  H01L29/7802

    Abstract: A termination structure for a superjunction device on which the net charge between P pylons in an Nnull termination region is intentionally unbalanced and is negative. The P pylons in the termination area are further non-uniformly located relative to those in the active area. A field ring which is an extension of the source electrode terminates at a radial mid point of the termination region.

    Abstract translation: 用于超结装置的端接结构，其中N-端接区域中的P型塔架之间的净电荷有意地不平衡并且是负的。 终端区域中的P型塔架相对于活动区域中的P型塔架进一步不均匀地定位。 作为源电极的延伸的场环在终止区域的径向中点终止。

    Digital dimming fluorescent ballast
    9.
    发明申请
    Digital dimming fluorescent ballast 有权
    数字调光荧光灯

    公开(公告)号：US20020158591A1

    公开(公告)日：2002-10-31

    申请号：US10108543

    申请日：2002-03-27

    Applicant: International Rectifier Corp.

    Inventor： Thomas J. Ribarich ,  Cecelia Contenti

    IPC: H05B037/02

    CPC classification number: H05B37/0254 ,  H05B41/2981 ,  H05B41/36 ,  H05B41/3921 ,  Y10S315/04

    Abstract: An electronic ballast circuit for powering a gas discharge lamp is networked with other ballast circuits to provide large scale lighting control on a local or remote basis. The ballast has an interface connectable to a standard PC for receiving commands and obtaining query information. The ballasts can be controlled individually or in groups. The ballast control also can download lighting profiles to a microcontroller in the ballast, and can support lighting control protocols including the DALI standard.

    Abstract translation: 用于为气体放电灯供电的电子镇流器电路与其他镇流器电路联网，以在本地或远程的基础上提供大规模照明控制。 镇流器具有可连接到标准PC的接口，用于接收命令和获取查询信息。 镇流器可以单独或分组控制。 镇流器控制还可以将照明配置文件下载到镇流器中的微控制器，并且可以支持包括DALI标准的照明控制协议。

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