公开(公告)号：US20030085422A1

公开(公告)日：2003-05-08

申请号：US10234303

申请日：2002-08-30

Applicant: International Rectifier Corp.

Inventor： Adam I. Amali ,  Naresh Thapar

IPC: H01L021/336 ,  H01L029/76 ,  H01L031/062

CPC classification number: H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66734 ,  H01L29/7811

Abstract: A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with the top of the silicon. Source regions of short lateral extent extend into the trench walls to a depth below the top of the polysilicon. A trench termination is formed having an insulation oxide liner covered by a polysilicon layer, covered in turn by a deposited oxide.

Abstract translation: 沟槽型功率MOS器件具有衬有氧化物并填充有导电多晶硅的多个隔开的沟槽。 多晶硅填料的顶部位于顶部硅表面之下，并用沉积的氧化物封盖，其顶部与硅的顶部齐平。 短横向范围的源区域延伸到沟槽壁中至多晶硅顶部的深度。 形成具有由多晶硅层覆盖的绝缘氧化物衬垫的沟槽端接，并且依次由被沉积的氧化物覆盖。

公开(公告)号：US20020163040A1

公开(公告)日：2002-11-07

申请号：US10138130

申请日：2002-05-02

Applicant: International Rectifier Corp.

Inventor： Daniel M. Kinzer ,  Tim Sammon ,  Mark Pavier ,  Adam I. Amali

IPC: H01L029/76

CPC classification number: H01L23/4952 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40137 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/8485 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A driver stage consisting of an N channel FET and a P channel FET are mounted in the same package as the main power FET. The power FET is mounted on a lead frame and the driver FETs are mounted variously on a separate pad of the lead frame or on the main FET or on the lead frame terminals. All electrodes are interconnected within the package by mounting on common conductive surfaces or by wire bonding. The drivers are connected to define either an inverting or non-inverting drive.

Abstract translation: 由N沟道FET和P沟道FET组成的驱动器级与主功率FET安装在同一封装中。 功率FET安装在引线框架上，驱动器FET分别安装在引线框架或主FET或引线框架端子的独立焊盘上。 所有电极通过安装在公共导电表面上或通过引线接合在封装内互连。 驱动器连接以定义反相或非反相驱动器。