公开(公告)号：US20020195627A1

公开(公告)日：2002-12-26

申请号：US09891727

申请日：2001-06-26

Applicant: International Rectifier Corp.

Inventor： Daniel M. Kinzer ,  Srikant Sridevan

IPC: H01L031/062

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/7824 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A lateral conduction superjunction semiconductor device has a plurality of spaced vertical trenches in a junction receiving layer of Pnull silicon. An Nnull diffusion lines the walls of the trench and the concentration and thickness of the Nnull diffusion and Pnull mesas are arranged to deplete fully in reverse blocking operation. A MOSgate structure is connected at one end of the trenches and a drain is connected at its other end. An Nnullnull further layer or an insulation oxide layer may be interposed between a Pnullnull substrate and the Pnull junction receiving layer.

Abstract translation: 横向导电超结半导体器件在P-硅的结接收层中具有多个间隔开的垂直沟槽。 N-扩散线排列在沟槽的壁上，并且N-扩散和P-台面的浓度和厚度被排列成完全消耗在反向阻塞操作中。 MOSgate结构在沟槽的一端连接，漏极在其另一端连接。 可以在P-基底和P-结接收层之间插入N-另外的层或绝缘氧化物层。

公开(公告)号：US20040065934A1

公开(公告)日：2004-04-08

申请号：US10649929

申请日：2003-08-26

Applicant: International Rectifier Corp.

Inventor： Srikant Sridevan ,  Daniel M. Kinzer

IPC: H01L023/58

CPC classification number: H01L29/0634 ,  H01L29/0847 ,  H01L29/0852 ,  H01L29/1095 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/78624 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A lateral conduction superjunction device has bidirectional conduction characteristics. In a first embodiment, spaced vertical trenches in a P substrate are lined with N diffusions. A central MOSgate structure is disposed centrally in the parallel trenches and source and drain electrodes are at the opposite respective ends of the trenches. In a second embodiment, flat layers of alternately opposite conductivity types have source and drain regions at their opposite ends. A trench MOSgate is disposed between the source region at one end of the layers to enable bidirectional currant flow through the stocked layers.

公开(公告)号：US20030062585A1

公开(公告)日：2003-04-03

申请号：US10254112

申请日：2002-09-25

Applicant: International Rectifier Corp.

Inventor： Kohji Andoh ,  Davide Chiola ,  Daniel M. Kinzer

IPC: H01L027/095

CPC classification number: H01L27/0814 ,  H01L29/66143 ,  H01L29/8725

Abstract: A Schottky diode has a barrier height which is adjusted by boron implant through a titanium silicide Schottky contact and into the underlying Nnull silicon substrate which receives the titanium silicide contact. The implant is a low energy, of about 10 keV (non critical) and a low dose of less than about 1E12 atoms per cm2 (non-critical).

Abstract translation: 肖特基二极管具有通过硼注入通过硅化钛肖特基接触并进入接收硅化钛接触的下面的N-硅衬底中的势垒高度。 植入物是约10keV（非临界）和小于约1E12原子/ cm 2（非关键）的低能量的低能量。

公开(公告)号：US20020163040A1

公开(公告)日：2002-11-07

申请号：US10138130

申请日：2002-05-02

Applicant: International Rectifier Corp.

Inventor： Daniel M. Kinzer ,  Tim Sammon ,  Mark Pavier ,  Adam I. Amali

IPC: H01L029/76

CPC classification number: H01L23/4952 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40137 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/8485 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A driver stage consisting of an N channel FET and a P channel FET are mounted in the same package as the main power FET. The power FET is mounted on a lead frame and the driver FETs are mounted variously on a separate pad of the lead frame or on the main FET or on the lead frame terminals. All electrodes are interconnected within the package by mounting on common conductive surfaces or by wire bonding. The drivers are connected to define either an inverting or non-inverting drive.

Abstract translation: 由N沟道FET和P沟道FET组成的驱动器级与主功率FET安装在同一封装中。 功率FET安装在引线框架上，驱动器FET分别安装在引线框架或主FET或引线框架端子的独立焊盘上。 所有电极通过安装在公共导电表面上或通过引线接合在封装内互连。 驱动器连接以定义反相或非反相驱动器。

公开(公告)号：US20010045635A1

公开(公告)日：2001-11-29

申请号：US09780080

申请日：2001-02-09

Applicant: International Rectifier Corp.

Inventor： Daniel M. Kinzer ,  Aram Arzumanyan ,  Tim Sammon

IPC: H01L023/495 ,  H01L023/02

CPC classification number: H01L29/7813 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/50 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/7809 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A flip-chip MOSFET structure has a vertical conduction semiconductor die in which the lower layer of the die is connected to a drain electrode on the top of the die by a diffusion sinker or conductive electrode. The source and gate electrodes are also formed on the upper surface of the die and have coplanar solder balls for connection to a circuit board. The structure has a chip scale package size. The back surface of the die, which is inverted when the die is mounted may be roughened or may be metallized to improve removal of heat from the die. Several separate MOSFETs can be integrated side-by-side into the die to form a series connection of MOSFETs with respective source and gate electrodes at the top surface having solder ball connectors. Plural solder ball connectors may be provided for the top electrodes and are laid out in respective parallel rows. The die may have the shape of an elongated rectangle with the solder balls laid out symmetrically to a diagonal to the rectangle.

Abstract translation: 倒装芯片MOSFET结构具有垂直导电半导体管芯，其中管芯的下层通过扩散沉积片或导电电极连接到管芯顶部的漏电极。 源极和栅电极也形成在管芯的上表面上，并且具有用于连接到电路板的共面焊球。 该结构具有芯片级封装尺寸。 当安装模具时倒模的模具的背面可以被粗糙化或者可以被金属化以改善从模具中的热量的去除。 几个单独的MOSFET可以并排集成到管芯中，以形成MOSFET与具有焊球连接器的顶表面处的相应源极和栅电极的串联连接。 可以为顶部电极提供多个焊球连接器并且布置在各自的平行行中。 模具可以具有细长矩形的形状，其中焊球对称地对准矩形的对角线。