公开(公告)号：US20020096748A1

公开(公告)日：2002-07-25

申请号：US10050002

申请日：2002-01-15

Applicant: International Rectifier Corp.

Inventor： Mark Pavier

IPC: H01L023/495

CPC classification number: H01L24/49 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A small footprint package for two or more semiconductor die includes first and second die, mounted on opposite respective surfaces of a lead frame pad in vertical alignment with one another. A conductive or insulation adhesive can be used. The die can be identical MOSgated devices connected in series, or can be one power die and a second IC die for the control of the power die.

Abstract translation: 用于两个或更多个半导体管芯的小尺寸封装包括第一和第二管芯，其安装在彼此垂直对准的引线框架焊盘的相对的相对表面上。 可以使用导电或绝缘粘合剂。 芯片可以是串联连接的相同的MOS器件，或者可以是一个功率管芯和用于控制功率管芯的第二个IC管芯。

公开(公告)号：US20030062622A1

公开(公告)日：2003-04-03

申请号：US10260148

申请日：2002-09-27

Applicant: International Rectifier Corp.

Inventor： Mark Pavier ,  Tim Sammon

IPC: H01L023/48

CPC classification number: H01L29/7811 ,  H01L23/3677 ,  H01L24/81 ,  H01L27/088 ,  H01L29/7809 ,  H01L29/7813 ,  H01L2224/81801 ,  H01L2924/01068 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

Abstract: A flip chip structure contains laterally spaced semiconductor devices such as MOSFETs in a common chip. A deep trench isolates the devices. Contacts are connected to the source drain and gate electrode (or other electrodes) and are interconnected as required for a circuit function either within the chip or on the support board. Ball contacts are connected to the electrodes. The opposite surface of the chip to that in which the devices are formed receives a copper or other metal layer which is patterned to increase its area for heat exchange. The surface of the copper is coated with black oxide to increase its ability to radiate heat.

Abstract translation: 倒装芯片结构包含横向​​间隔的半导体器件，例如公共芯片中的MOSFET。 深沟渠隔离设备。 触点连接到源极漏极和栅电极（或其他电极），并且根据芯片或支撑板上的电路功能的要求进行互连。 球触点连接到电极。 芯片的与形成器件的相对表面接收铜或其它金属层，其被图案化以增加其用于热交换的面积。 铜的表面涂覆有黑色氧化物以增加其辐射热能力。

公开(公告)号：US20030165072A1

公开(公告)日：2003-09-04

申请号：US10090281

申请日：2002-03-04

Applicant: International Rectifier Corp.

Inventor： Bruno C. Nadd ,  David C. Tam ,  Mark Pavier ,  Glyn Connah

IPC: H02M001/00

CPC classification number: H02P29/02 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/13055 ,  H01L2924/13091 ,  H02M1/32 ,  H02M1/36 ,  H02M1/38 ,  H02M7/003 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A fully protected H-bridge for a d-c motor consists of two high side MOSFETs and a control and logic IC on a first conductive heat sink all within a first package and two discrete low side MOSFETs. The entire bridge is controlled by the IC. Shoot thru protection is provided for each leg, and a PMW soft start sequence is provided through the control of the low side MOSFETs, programed by an external, chargeable RC circuit. Input signals to the high side MOSFETs select the operation modes. Protective circuits are provided for short circuit current and over current conditions. Sleep mode and braking/non braking control is also provided.

Abstract translation: 用于d-c电机的完全受保护的H桥由两个高边MOSFET组成，第一导电散热器上的控制和逻辑IC都在第一封装和两个分立的低侧MOSFET内。 整个桥梁由IC控制。 为每条支路提供射击保护，通过控制低端MOSFET提供PMW软起动序列，由外部可充电RC电路编程。 输入高边MOSFET的信号选择工作模式。 为短路电流和过流条件提供保护电路。 还提供睡眠模式和制动/非制动控制。

公开(公告)号：US20020163040A1

公开(公告)日：2002-11-07

申请号：US10138130

申请日：2002-05-02

Applicant: International Rectifier Corp.

Inventor： Daniel M. Kinzer ,  Tim Sammon ,  Mark Pavier ,  Adam I. Amali

IPC: H01L029/76

CPC classification number: H01L23/4952 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40137 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/8485 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A driver stage consisting of an N channel FET and a P channel FET are mounted in the same package as the main power FET. The power FET is mounted on a lead frame and the driver FETs are mounted variously on a separate pad of the lead frame or on the main FET or on the lead frame terminals. All electrodes are interconnected within the package by mounting on common conductive surfaces or by wire bonding. The drivers are connected to define either an inverting or non-inverting drive.

Abstract translation: 由N沟道FET和P沟道FET组成的驱动器级与主功率FET安装在同一封装中。 功率FET安装在引线框架上，驱动器FET分别安装在引线框架或主FET或引线框架端子的独立焊盘上。 所有电极通过安装在公共导电表面上或通过引线接合在封装内互连。 驱动器连接以定义反相或非反相驱动器。