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    Reversed source-drain mosgated device
    1.
    发明申请
    Reversed source-drain mosgated device 有权
    反向源极漏极mosgated器件

    公开(公告)号：US20020036318A1

    公开(公告)日：2002-03-28

    申请号：US09907262

    申请日：2001-07-17

    Applicant: International Rectifier Corp.

    Inventor： Naresh Thapar

    IPC: H01L029/80

    CPC classification number: H01L29/781 ,  H01L29/7827

    Abstract: A MOSgated device with a minimum overlap between the gate and drain electrodes is comprised of an Nnull substrate which receives an epitaxial layer of silicon. The body of the epitaxial layer has an N- lower layer for an accumulation device or a Pnull drift lower layer. In each case the top of the epitixial layer is Nnull. Both can be operated in an a-c mode. A trench gate consists of a trench through the epitaxial layer which has a thin gate oxide layer on its walls and bottom and a conductive polysilicon gate body filling the trench. The thin oxide on the bottom of the trench may be thicker than the oxide on the walls to reduce gate capacitance. A thick isolation oxide which is about 10 times as thick as the gate oxide overlies the top of the polysilicon. A planar drain electrode overlies the Nnull top layer and the laterally spaced isolation oxide; and a planar source electrode contacts the bottom of the substrate.

    Abstract translation: 栅极和漏极之间具有最小重叠的MOS器件由接纳硅外延层的N +衬底构成。 外延层的主体具有用于累积装置或P-漂移下层的N-下层。 在每种情况下，上皮层的顶部是N +。 两者都可以在a-c模式下操作。 沟槽栅由通过外延层的沟槽组成，其沟槽在其壁和底部具有薄的栅极氧化物层，以及填充沟槽的导电多晶硅栅极体。 沟槽底部的薄氧化物可以比壁上的氧化物厚，以减小栅极电容。 厚度约为栅极氧化物厚度的10倍的厚隔离氧化物覆盖多晶硅的顶部。 平面漏极覆盖在N +顶层和横向隔开的隔离氧化物上; 并且平面源电极接触衬底的底部。

    Low voltage power MOSFET device and process for its manufacture
    2.
    发明申请
    Low voltage power MOSFET device and process for its manufacture 有权
    低压功率MOSFET器件及其制造工艺

    公开(公告)号：US20010026989A1

    公开(公告)日：2001-10-04

    申请号：US09814087

    申请日：2001-03-21

    Applicant: International Rectifier Corp.

    Inventor： Naresh Thapar

    IPC: H01L021/76

    CPC classification number: H01L29/7813 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368

    Abstract: A trench type power MOSFET has a thin vertical gate oxide along its side walls and a thickened oxide with a rounded bottom at the bottom of the trench to provide a low RDSON and increased VDSMAX and VGSMAX and a reduced Miller capacitance. The walls of the trench are first lined with nitride to permit the growth of the thick bottom oxide to, for example 1000 null to 1400 null and the nitride is subsequently removed and a thin oxide, for example 320 null is regrown on the side walls. In another embodiment, the trench bottom in amorphized and the trench walls are left as single crystal silicon so that oxide can be grown much faster and thicker on the trench bottom than on the trench walls during an oxide growth step. A reduced channel length of about 0.7 microns is used. The source diffusion is made deeper than the implant damage depth so that the full 0.7 micron channel is along undamaged silicon. A very lightly doped diffusion of 1000 null to 2000 null in depth could also be formed around the bottom of the trench and is depleted at all times by the inherent junction voltage to further reduce Miller capacitance and switching loss.

    Abstract translation: 沟槽型功率MOSFET沿其侧壁具有薄的垂直栅极氧化物，并且在沟槽底部具有圆形底部的增厚氧化物，以提供低RDSON和增加的VDSMAX和VGSMAX以及降低的米勒电容。 沟槽的壁首先衬有氮化物以允许将厚的底部氧化物生长至例如1000埃至1400埃，随后除去氮化物，并且在侧壁上重新生长例如320埃的薄氧化物。 在另一个实施例中，非晶化的沟槽底部和沟槽壁留作单晶硅，使得在氧化物生长步骤期间，沟槽底部的氧化物可以比在沟槽壁上生长得更快更厚。 使用约0.7微米的减小的通道长度。 源扩散比植入物损伤深度更深，使得完整的0.7微米通道沿着未损坏的硅。 还可以在沟槽的底部周围形成深度为1000埃至2000埃的非常轻微掺杂的扩散，并且随时通过固有结电压耗尽，以进一步降低米勒电容和开关损耗。

    Trench fet with self aligned source and contact
    3.
    发明申请
    Trench fet with self aligned source and contact 有权
    具有自对准源和接触的沟槽胎

    公开(公告)号：US20030085422A1

    公开(公告)日：2003-05-08

    申请号：US10234303

    申请日：2002-08-30

    Applicant: International Rectifier Corp.

    Inventor： Adam I. Amali ,  Naresh Thapar

    IPC: H01L021/336 ,  H01L029/76 ,  H01L031/062

    CPC classification number: H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66734 ,  H01L29/7811

    Abstract: A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with the top of the silicon. Source regions of short lateral extent extend into the trench walls to a depth below the top of the polysilicon. A trench termination is formed having an insulation oxide liner covered by a polysilicon layer, covered in turn by a deposited oxide.

    Abstract translation: 沟槽型功率MOS器件具有衬有氧化物并填充有导电多晶硅的多个隔开的沟槽。 多晶硅填料的顶部位于顶部硅表面之下，并用沉积的氧化物封盖，其顶部与硅的顶部齐平。 短横向范围的源区域延伸到沟槽壁中至多晶硅顶部的深度。 形成具有由多晶硅层覆盖的绝缘氧化物衬垫的沟槽端接，并且依次由被沉积的氧化物覆盖。

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