公开(公告)号：US20030205829A1

公开(公告)日：2003-11-06

申请号：US10138164

申请日：2002-05-01

Applicant: International Rectifier Corp.

Inventor： Milton J. Boden JR.

IPC: H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/113 ,  H01L031/119

CPC classification number: H01L29/7802 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095

Abstract: A Rad Hard MOSFET has a plurality of closely spaced base strips which have respective source to form invertible surface channels with the opposite sides of each of the stripes. A non-DMOS late gate oxide and overlying conductive polysilicon gate are formed after the source and base regions have been diffused. The base strips are spaced by about 0.6 microns, and the polysilicon gate stripes are about 3.2 microns wide. An enhancement region is implanted through spaced narrow window early in the process and are located in the JFET common conduction region which is later formed by and between the spaced base stripes. The device is a high voltage (greater than 25 volts) device with very low gate capacitance and very low on resistance. An early and deep (1.6 micron) P channel implant and diffusion are formed before the main channel is formed to produce a graded body diode junction.

Abstract translation: Rad硬MOSFET具有多个紧密间隔的基带，其具有相应的源以与每个条的相对侧形成可逆表面通道。 在源极和基极区域扩散之后形成非DMOS后栅极氧化物和上覆导电多晶硅栅极。 基带间隔约0.6微米，多晶硅栅极条宽约3.2微米。 增强区域在该过程的早期通过间隔窄的窗口注入并且位于JFET共同导电区域中，后者由隔开的基底条纹之间和之间形成。 该器件是具有非常低栅极电容和非常低导通电阻的高电压（大于25伏特）器件。 在形成主通道之前形成早期和深（1.6微米）的P沟道注入和扩散以产生分级体二极管结。

公开(公告)号：US20040016945A1

公开(公告)日：2004-01-29

申请号：US10205125

申请日：2002-07-23

Applicant: International Rectifier Corp.

Inventor： Milton J. Boden JR.

IPC: H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/113 ,  H01L031/119

CPC classification number: H01L29/7802 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/66712

Abstract: A P channel vertical conduction Rad Hard MOSFET has a plurality of closely spaced base strips which have respective sources to form invertible surface channels with the opposite sides of each of the stripes. A non-DMOS late gate oxide and overlying conductive polysilicon gate are formed after the source and base regions have been diffused. The base stripes are spaced by about 0.6 microns, and the polysilicon gate stripes are about 3.2 microns wide. A P type enhancement region is implanted through spaced narrow windows early in the process and are located in the JFET common conduction region which is later formed by and between the spaced base stripes. The device is a high voltage (greater than 25 volts) P channel device with very low gate capacitance and very low on resistance.

Abstract translation: P沟道垂直导电Rad Hard MOSFET具有多个紧密间隔的基带，其具有各自的源以与每个条纹的相对侧形成可逆表面通道。 在源极和基极区域扩散之后形成非DMOS后栅极氧化物和上覆导电多晶硅栅极。 基条间隔约0.6微米，多晶硅栅极条宽约为3.2微米。 P型增强区域在工艺早期通过间隔窄的窗口植入，并且位于JFET共同导电区域中，后者由间隔开的基底条纹之间和之间形成。 该器件是具有非常低栅极电容和非常低导通电阻的高电压（大于25伏特）P沟道器件。