Mosfet with reduced threshold voltage and on resistance and process for its manufacture
    2.
    发明申请
    Mosfet with reduced threshold voltage and on resistance and process for its manufacture 有权
    Mosfet具有降低的阈值电压和电阻及其制造工艺

    公开(公告)号:US20030089945A1

    公开(公告)日:2003-05-15

    申请号:US10044427

    申请日:2001-11-09

    CPC classification number: H01L29/7802 H01L29/0847 H01L29/1095 H01L29/41766

    Abstract: A vertical conduction MOSFET having a reduced on resistance RDSON as well as reduced threshold voltage Vth, and an improved resistance to punchthrough and walkout has an extremely shallow source diffusion, of less than 0.3 microns in depth and an extremely shallow channel diffusion, of less than about 3 microns in depth. In a P channel version, phosphorus is implanted into the bottom of a contact trench and into the channel region with an implant energy of 400 keV for a singly charged phosphorus ion or 200 keV for a doubly charged ion, thereby to prevent walkout of the threshold voltage.

    Abstract translation: 具有降低的导通电阻RDSON和降低的阈值电压Vth的垂直导通MOSFET以及改进的穿通和迂回阻力具有小于0.3微米深度的极浅源极扩散和小于0.3微米的通道扩散。 约3微米深。 在P沟道版本中,磷被注入到接触沟槽的底部并且注入到沟道区域中,对于单电荷的磷离子或200keV的注入能量为400keV,用于双电荷离子,从而防止阈值 电压。

    Reduced mask count process for manufacture of mosgated device
    3.
    发明申请
    Reduced mask count process for manufacture of mosgated device 有权
    减少遮阳装置的掩模计数过程

    公开(公告)号:US20020137322A1

    公开(公告)日:2002-09-26

    申请号:US10094835

    申请日:2002-03-07

    Abstract: A process for forming a power MOSFET enables the connection a metal gate electrode to the conductive polysilicon gates in the active area without an additional mask step. In the process, a groove is formed in the field oxide during the active area mask step. Conductive polysilicon is then formed over the active area and into the groove. At least one window is formed over the groove along with the mask window for forming the channel and source implant windows, and the polysilicon is etched to the silicon surface in the active area, but a strip is left in the groove. This strip is contacted by gate metal during metal deposition. Thus, gate metal is connected to the polysilicon without an added mask step.

    Abstract translation: 用于形成功率MOSFET的工艺使得能够在没有额外的掩模步骤的情况下将金属栅电极连接到有源区中的导电多晶硅栅极。 在该过程中,在有源区掩模步骤期间,在场氧化物中形成凹槽。 然后在有源区域上形成导电多晶硅并进入沟槽。 至少一个窗口与用于形成沟道和源植入窗口的掩模窗口一起形成在沟槽上方,并且多晶硅被蚀刻到有源区域中的硅表面,但是条带留在沟槽中。 在金属沉积期间,该带与栅极金属接触。 因此,栅极金属连接到多晶硅而没有添加掩模步骤。

    Depletion implant for power MOSFET
    5.
    发明申请
    Depletion implant for power MOSFET 有权
    功耗MOSFET消耗植入

    公开(公告)号:US20020117687A1

    公开(公告)日:2002-08-29

    申请号:US10083060

    申请日:2002-02-26

    Abstract: A vertical MOSFET has a substrate of a first conductivity type. A channel region of a second conductivity type is diffused into the substrate. A gate is disposed at least partially over the channel region. A source region of a second conductivity type is disposed proximate to the gate and adjacent to the channel region. The channel region includes a depletion implant area proximate to the gate. The depletion implant species is of the second conductivity type to reduce the concentration of the first conductivity type in the channel region without increasing the conductivity in the drain/drift region.

    Abstract translation: 垂直MOSFET具有第一导电类型的衬底。 第二导电类型的沟道区域扩散到衬底中。 至少部分地在通道区域上设置栅极。 第二导电类型的源极区域设置在栅极附近并且邻近沟道区域。 沟道区域包括靠近栅极的耗尽植入区域。 耗尽注入种类具有第二导电类型,以减小沟道区中第一导电类型的浓度,而不增加漏极/漂移区中的导电性。

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