公开(公告)号：US20040266220A1

公开(公告)日：2004-12-30

申请号：US10900780

申请日：2004-07-28

申请人： Micron Technology, Inc.

发明人： Kie Y. Ahn ,  Leonard Forbes

IPC分类号： H01L021/336 ,  H01L021/4763 ,  H01L021/31 ,  H01L021/469

CPC分类号： H01L28/82 ,  C23C14/10 ,  C23C14/226 ,  H01L21/02164 ,  H01L21/02203 ,  H01L21/02263 ,  H01L21/31695 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure that includes a vapor-deposited dielectric material. The dielectric material has a predetermined microstructure formed using a glancing angle deposition (GLAD) process. The microstructure includes columnar structures that provide a porous dielectric material. One aspect is a method of forming a low-k insulator structure. In one embodiment, a predetermined vapor flux incidence angle null is set with respect to a normal vector for a substrate surface so as to promote a dielectric microstructure with individual columnar structures. Vapor deposition and substrate motion are coordinated so as to form columnar structures in a predetermined shape. Other aspects are provided herein.

公开(公告)号：US20040266177A1

公开(公告)日：2004-12-30

申请号：US10895144

申请日：2004-07-21

申请人： Kabushiki Kaisha Toshiba

发明人： Masayuki Tanaka ,  Shigehiko Saida ,  Yoshitaka Tsunashima

IPC分类号： H01L021/4763

CPC分类号： H01L21/0217 ,  H01L21/02208 ,  H01L21/02211 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/10873 ,  H01L2924/0002 ,  H01L2924/00

摘要： Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.

摘要翻译： 使用六氯二硅烷（Si 2 Cl 6）作为用于形成可能与氧化硅膜的蚀刻速率差异很大的氮化硅膜的Si原料。 氮化硅膜通过LPCVD法形成。

公开(公告)号：US20040266174A1

公开(公告)日：2004-12-30

申请号：US10608347

申请日：2003-06-27

发明人： Chin-Tien Yang ,  Juei-Kuo Wu ,  Dian-Hua Chen ,  Huan-Chi Tseng

IPC分类号： H01L021/4763 ,  H01L021/44

CPC分类号： H01L21/7684

摘要： A method of reducing or substantially eliminating the number of tungsten plug pullouts and consequential chip failures by controlling the CMP step of removing the overfilled tungsten so as to leave a thin layer of tungsten instead of continuing the removal down to the top surface of the dielectric layer.

摘要翻译： 通过控制CMP步骤来去除过度填充的钨以便留下薄层的钨而不是继续去除介电层的顶表面，从而减少或基本上消除了钨丝塞拉出次数和后果的芯片故障的方法 。

公开(公告)号：US20040266151A1

公开(公告)日：2004-12-30

申请号：US10725320

申请日：2003-12-02

发明人： Kwan-Yong Lim ,  Heung-Jae Cho ,  Jung-Ho Lee ,  Se-Aug Jang ,  Yong-Soo Kim ,  Byung-Seop Hong ,  Jae-Geun Ho ,  Hong-Seon Yang ,  Hyun-Chul Sohn

IPC分类号： H01L021/3205 ,  H01L021/4763 ,  H01L021/44

CPC分类号： H01L21/2807 ,  H01L29/4941

摘要： The present invention relates to a method for fabricating a gate electrode of a semiconductor device with a double hard mask capable of preventing an abnormal oxidation of a metal layer included in the gate electrode and suppressing stress generation. The method includes the steps of: forming a gate insulation layer on a substrate; forming a gate layer structure containing at least a metal layer on the gate insulation layer; forming a hard mask oxide layer on the gate layer structure at a temperature lower than an oxidation temperature of the metal layer; forming a hard mask nitride layer on the hard mask oxide layer; patterning the hard mask oxide layer and the hard mask nitride layer as a double hard mask for forming the gate electrode; and forming the gate electrode by etching the gate layer structure with use of the double hard mask as an etch mask.

摘要翻译： 本发明涉及一种制造半导体器件的栅电极的方法，所述半导体器件具有能够防止包含在栅极电极中的金属层的异常氧化并抑制应力产生的双重硬掩模。 该方法包括以下步骤：在衬底上形成栅极绝缘层; 在所述栅极绝缘层上形成至少含有金属层的栅极层结构; 在低于金属层的氧化温度的温度下在栅极层结构上形成硬掩模氧化物层; 在硬掩模氧化物层上形成硬掩模氮化物层; 将硬掩模氧化物层和硬掩模氮化物层图案化为用于形成栅电极的双重硬掩模; 以及通过使用双重硬掩模作为蚀刻掩模蚀刻栅极层结构来形成栅电极。

公开(公告)号：US20040266117A1

公开(公告)日：2004-12-30

申请号：US10850473

申请日：2004-05-19

发明人： Hyun Sang Hwang

IPC分类号： H01L021/336 ,  H01L021/3205 ,  H01L021/4763

CPC分类号： H01L21/28176 ,  H01L21/28194 ,  H01L21/3003 ,  H01L21/3141 ,  H01L29/51 ,  H01L29/517

摘要： Disclosed is a method of manufacturing a high-k gate dielectric, characterized in that an annealing process in a forming gas atmosphere, corresponding to a final step of a manufacturing process of a semiconductor device based on MOSFET fabrication techniques, is applied for a high-k gate dielectric-containing semiconductor device, under high pressure, instead of conventional atmospheric pressure, whereby passivation effects of interface charges and fixed charges of the semiconductor device can be maximized even at relatively low temperatures.

摘要翻译： 公开了一种制造高k栅极电介质的方法，其特征在于，对应于基于MOSFET制造技术的半导体器件的制造工艺的最后步骤，形成气体气氛中的退火工艺被应用于高k栅极电介质， k栅极电介质的半导体器件，而不是常规的大气压，由此即使在相对低的温度下也可以使半导体器件的界面电荷和固定电荷的钝化效果最大化。

公开(公告)号：US20040259344A1

公开(公告)日：2004-12-23

申请号：US10830896

申请日：2004-04-22

发明人： Dong-Kyun Park ,  Ju-Cheol Shin ,  Hyeon-Deok Lee ,  In-Sun Park ,  Hyun-Seok Lim

IPC分类号： H01L021/28 ,  H01L021/3205 ,  H01L021/20 ,  H01L021/4763

CPC分类号： C23F1/12 ,  H01L21/32115 ,  H01L21/32136 ,  H01L21/76838 ,  H01L21/7684

摘要： A preliminary metal layer having a first thickness is formed on a substrate. A surface of the preliminary metal layer having uneven portions is etched to remove the uneven portions and to form a metal layer having an improved surface morphology. Therefore, shorts caused by the surface morphology of a metal layer occur less frequently and the semiconductor fabricating yield improves.

摘要翻译： 在基板上形成具有第一厚度的初步金属层。 蚀刻具有不平坦部分的预备金属层的表面以去除不平坦部分并形成具有改善的表面形态的金属层。 因此，由金属层的表面形态引起的短路发生得较少，半导体制造成品率提高。

公开(公告)号：US20040253775A1

公开(公告)日：2004-12-16

申请号：US10459495

申请日：2003-06-12

发明人： Krishnashree Achuthan ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC分类号： H01L021/336 ,  H01L021/8234 ,  H01L021/4763 ,  H01L021/461

CPC分类号： H01L29/785 ,  C09G1/02 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/6681 ,  Y10S438/959

摘要： A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial nullroughnull planarization and then a nullfinenull planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.

摘要翻译： 制造MOSFET型半导体器件的方法包括平坦化沉积在沟道上的栅极材料层。 平面化在包括初始“粗糙”平坦化然后是“精细”平坦化的多步骤过程中进行。 用于更精细平坦化的浆料可以包括倾向于粘附到栅极材料的低区域的添加材料。

公开(公告)号：US20040248407A1

公开(公告)日：2004-12-09

申请号：US10455650

申请日：2003-06-05

发明人： Chi-Wen Liu ,  Ying-Lang Wang

IPC分类号： H01L021/4763

CPC分类号： H01L21/288 ,  H01L21/7684 ,  H01L21/76879

摘要： A damascene-formed conductive region having a recess formed at the top surface thereof by a chemical-mechanical polish (CMP) process is repaired or regrown using a displacement method. A displacement material is deposited over the recessed conductive material. The displacement material is removed from a top surface of the insulating layer surrounding the damascene conductive region, and the semiconductor device is placed in a solution. The displacement material reacts with the solution, and copper in the solution is grown as a result of the displacement over the recess of the conductive region. The displacement method results in reducing or eliminating the recess formed by the CMP process.

摘要翻译： 通过化学机械抛光（CMP）工艺在其顶表面形成具有凹陷的镶嵌形成的导电区域使用位移法进行修复或重新生长。 位移材料沉积在凹陷的导电材料上。 从位于镶嵌导电区域的绝缘层的上表面除去位移材料，将半导体器件置于溶液中。 位移材料与溶液反应，并且溶液中的铜由于在导电区域的凹部上的位移而生长。 位移法导致减少或消除由CMP工艺形成的凹槽。

公开(公告)号：US20040248406A1

公开(公告)日：2004-12-09

申请号：US10861863

申请日：2004-06-04

发明人： Sung-Un Kwon ,  Yong-Sun Ko

IPC分类号： H01L021/4763 ,  H01L021/44

CPC分类号： H01L21/76831 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76895

摘要： A Local interconnection wiring structure method for forming the same reduces the likelihood of a short between a local interconnection layer of gate electrodes and an active region by forming a common aperture so as to have a determined aperture between the local interconnection layer and the active region on an insulation film of a semiconductor substrate. Methods of forming the local interconnection wire can include forming a first etching mask pattern that has a size longer than a length between inner ends of adjacent gate electrodes formed on a semiconductor substrate and covered with an insulation film. The etching mask simultaneously has a length the same as or shorter than the length between outer ends of the gate electrodes. The insulation film exposed in the first etching mask pattern is subsequently etched so that the insulation film remains higher than a highest height of the gate electrodes, so as to form a recess pattern. The first etching mask pattern is then removed and a second etching mask pattern is formed so as to partially expose the insulation film provided within the recess pattern. The insulation film within the recess pattern is etched to form apertures for exposing a partial surface of the gate electrodes. The second etching mask pattern is then removed. The recess pattern and the apertures are then filled with conductive material to form a local interconnection layer for connecting between the gate electrodes.

摘要翻译： 用于形成本发明的局部互连布线结构方法通过形成公共孔径来减小栅电极的局部互连层和有源区之间的短路的可能性，以便在局部互连层和有源区之间具有确定的孔径 半导体衬底的绝缘膜。 形成局部互连线的方法可以包括形成第一蚀刻掩模图案，其具有比形成在半导体衬底上并被绝缘膜覆盖的相邻栅电极的内端之间的长度的长度。 蚀刻掩模同时具有与栅电极的外端之间的长度相同或更短的长度。 随后蚀刻在第一蚀刻掩模图案中暴露的绝缘膜，使得绝缘膜保持高于栅电极的最高高度，以形成凹陷图案。 然后去除第一蚀刻掩模图案，并且形成第二蚀刻掩模图案，以便部分地暴露设置在凹槽图案内的绝缘膜。 蚀刻凹槽图形内的绝缘膜以形成用于暴露栅电极的局部表面的孔。 然后去除第二蚀刻掩模图案。 然后用导电材料填充凹槽图案和孔，以形成用于连接栅电极的局部互连层。

公开(公告)号：US20040248401A1

公开(公告)日：2004-12-09

申请号：US10859217

申请日：2004-06-03

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Mitsunari Satake ,  Muneyuki Matsumoto

IPC分类号： H01L021/4763

CPC分类号： H01L21/7684 ,  C09G1/02 ,  H01L21/3212

摘要： A TaN film and a Cu film are deposited successively over an insulating film formed with trenches. Then, a first CMP process is performed by using a slurry having a polishing rate for Cu sufficiently higher than a polishing rate for TaN and containing an agent for forming a protective film for Cu in a sufficient amount. As a result, the upper surface of the portion of the Cu film located in each of the trenches is positioned flush with the upper surface of TaN. Then, a second CMP process is performed under such a condition that the polishing rate for Cu is equal to or higher than the polishing rate for TaN, thereby forming Cu wires. By properly changing conditions for the second CMP process in accordance with the level of the upper surface of the Cu film, the upper surface of the Cu film is positioned flush with or lower in level than the upper surface of the insulating film after the second CMP process so that the occurrence of defective wiring is reduced.

摘要翻译： 在形成有沟槽的绝缘膜上依次沉积TaN膜和Cu膜。 然后，通过使用足够高于对TaN的研磨速度的Cu的抛光速率并且含有足够量的用于形成Cu的保护膜的试剂的浆料进行第一CMP工艺。 结果，位于每个沟槽中的Cu膜的部分的上表面与TaN的上表面齐平。 然后，在Cu的研磨速度为TaN的研磨速度以上的条件下进行第二CMP工序，从而形成Cu线。 通过根据Cu膜的上表面的水平适当地改变第二CMP工艺的条件，在第二CMP之后，Cu膜的上表面与绝缘膜的上表面齐平或更低 处理，从而减少了布线不良的发生。