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公开(公告)号：US09466367B2
公开(公告)日：2016-10-11
申请号：US15131142
申请日：2016-04-18
发明人： Kenichi Murooka
CPC分类号： G11C13/0069 , G06F3/0611 , G06F3/0659 , G06F3/0673 , G11C7/1006 , G11C13/0002 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C2213/71 , H01L27/2454 , H01L27/249 , H01L45/16
摘要： A memory device according to an embodiment comprises a data processing circuit that includes: a data write pre-processing circuit that processes input data to generate first intermediate data; a data write processing circuit that sequentially sets a voltage difference between a selected row line and a selected global bit line based on the first intermediate data; a data read processing circuit that detects a current flowing in the selected global bit line or a voltage of the selected global bit line and sequentially generates second intermediate data from a result of that detection; and a data read post-processing circuit that processes the second intermediate data to generate output data, the data write pre-processing circuit and the data read post-processing circuit having a correcting function that corrects a difference that may occur between the input data and the output data.
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公开(公告)号：US09455257B2
公开(公告)日：2016-09-27
申请号：US14593344
申请日：2015-01-09
发明人： Kenichi Murooka
IPC分类号： H01L27/10 , H01L27/105 , H01L27/24 , H01L45/00
CPC分类号： H01L27/249 , G11C13/0026 , G11C13/0028 , H01L27/1052 , H01L27/2454 , H01L27/2463 , H01L45/04 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A connection unit is provided adjacently to the cell array unit and electrically connected to a peripheral circuit unit positioned downwardly of the cell array unit. The cell array unit has a configuration in which a variable resistance layer is provided at intersections of a plurality of word lines extending in a horizontal direction and a plurality of bit lines extending in a vertical direction. The connection unit includes a lower wiring line layer in which a base portion bundling a plurality of the word lines is formed, and a middle wiring line layer and upper wiring line layer formed upwardly thereof. The lower wiring line layer includes: a first penetrating electrode connecting the plurality of word lines and the peripheral circuit unit; and a second penetrating electrode connecting at least one of the middle wiring line layer and upper wiring line layer and the peripheral circuit unit.
摘要翻译： 连接单元靠近单元阵列单元设置并电连接到位于单元阵列单元下方的外围电路单元。 电池阵列单元具有在水平方向上延伸的多个字线和在垂直方向上延伸的多个位线的交叉处设置可变电阻层的结构。 连接单元包括形成有多个字线的基部的下布线层，以及向上形成的中间布线线层和上布线线层。 下布线层包括：连接多条字线和外围电路单元的第一穿透电极; 以及连接中间布线层和上布线层和外围电路单元中的至少一个的第二贯穿电极。
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83.发明授权Array of nonvolatile memory cells having at least five memory cells per unit cell, having a plurality of the unit cells which individually comprise three elevational regions of programmable material, and/or having a continuous volume having a combination of a plurality of vertically oriented memory cells and a plurality of horizontally oriented memory cells; array of vertically stacked tiers of nonvolatile memory cells 有权具有每个单位单元具有至少五个存储单元的非易失性存储单元的阵列，具有单独包含可编程材料的三个高度区域的多个单位单元，和/或具有多个垂直取向的存储单元的组合的连续体积 和多个水平定向的存储单元; 非易失性存储单元的垂直层叠阵列公开(公告)号：US09454997B2
公开(公告)日：2016-09-27
申请号：US12959015
申请日：2010-12-02
申请人： Jun Liu
发明人： Jun Liu
CPC分类号： G11C5/02 , G11C13/0002 , G11C2213/71 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/14 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147
摘要： Disclosed is an array of nonvolatile memory cells includes five memory cells per unit cell. Also disclosed is an array of vertically stacked tiers of nonvolatile memory cells that includes five memory cells occupying a continuous horizontal area of 4F2 within an individual of the tiers. Also disclosed is an array of nonvolatile memory cells comprising a plurality of unit cells which individually comprise three elevational regions of programmable material, the three elevational regions comprising the programmable material of at least three different memory cells of the unit cell. Also disclosed is an array of vertically stacked tiers of nonvolatile memory cells that includes a continuous volume having a combination of a plurality of vertically oriented memory cells and a plurality of horizontally oriented memory cells. Other embodiments and aspects are disclosed.
摘要翻译： 公开了一种非易失性存储单元的阵列，每个单元具有五个存储单元。 还公开了一种非易失性存储器单元的垂直堆叠层的阵列，其包括在层的个体内占据4F2的连续水平面积的五个存储单元。 还公开了一种非易失性存储单元的阵列，其包括单独包含可编程材料的三个高程区域的多个单位单元，所述三个高程区域包括该单位单元的至少三个不同存储单元的可编程材料。 还公开了一种垂直堆叠的非易失性存储单元的阵列，其包括具有多个垂直取向的存储器单元和多个水平定向的存储器单元的组合的连续体积。 公开了其它实施例和方面。
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84.发明申请METHOD OF OPERATING MEMORY ARRAY HAVING DIVIDED APART BIT LINES AND PARTIALLY DIVIDED BIT LINE SELECTOR SWITCHES 有权具有分开的APART位线和部分分开的位线选择开关的存储器阵列的操作方法公开(公告)号：US20160268340A1
公开(公告)日：2016-09-15
申请号：US15161767
申请日：2016-05-23
CPC分类号： H01L27/249 , G11C5/025 , G11C7/18 , G11C8/12 , G11C13/0007 , G11C13/0009 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C13/025 , G11C2013/0078 , G11C2013/009 , G11C2213/32 , G11C2213/35 , G11C2213/71 , G11C2213/77 , G11C2213/78 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/149 , H01L45/16 , H01L45/1675
摘要： A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.
摘要翻译： 非易失性数据存储设备包括由相应和垂直取向的位线选择器单元独立驱动的一对立即相邻和隔离的另一局部位线。 紧邻和隔离的另一局部位线之间的隔离也将非易失性数据存储设备的彼此各自的存储单元隔离，使得漏电流不能从连接到紧邻的第一个的存储器单元流出 并且与另一个本地位线隔离到连接到一对立即相邻和隔离的另一局部位线中的第二个的存储器单元。 编程期望的存储器单元的方法包括对与期望的存储单元的位线相邻的字线施加升压电压，而不对与该对的另一位线相邻的字线施加升压电压。
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公开(公告)号：US20160268263A1
公开(公告)日：2016-09-15
申请号：US14734140
申请日：2015-06-09
申请人： SK hynix Inc.
发明人： Ki Hong LEE , Seung Ho PYI
IPC分类号： H01L27/115
CPC分类号： H01L27/11504 , H01L27/11507 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/10 , H01L45/1226 , H01L45/145 , H01L45/16
摘要： A semiconductor device includes a substrate in which a cell region and contact regions located at both sides of the cell region are defined, a first source layer formed over the substrate, a second source layer formed over the first source layer, a reinforcement pattern formed in the second source layer, a stacked structure including conductive layers and insulating layers alternately stacked over the second source layer and the reinforcement pattern, channel layers passing through the stacked structure and the second source layer and electrically coupled to the second source layer, and an isolation insulating pattern passing through at least one top conductive layer of the conductive layers.
摘要翻译： 一种半导体器件包括其中限定了单元区域和位于单元区域两侧的接触区域的基板，形成在基板上的第一源极层，形成在第一源极层上的第二源极层，形成在第一源极层 第二源极层，包括交替层叠在第二源极层和加强图案上的导电层和绝缘层的堆叠结构，穿过堆叠结构的沟道层和第二源极层，并且电耦合到第二源极层，以及隔离层 绝缘图案通过导电层的至少一个顶部导电层。
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公开(公告)号：US20160267968A1
公开(公告)日：2016-09-15
申请号：US14849023
申请日：2015-09-09
发明人： Kenichi MUROOKA
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/0002 , G11C13/0023 , G11C13/0026 , G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/77 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/1608
摘要： According to one embodiment, a memory device includes a plurality of first interconnects each provided along a first direction; a plurality of second interconnects each provided along the first direction; and a plurality of third interconnects each provided along a third direction that is different from the first direction.
摘要翻译： 根据一个实施例，存储器件包括多个第一互连件，每个第一互连件沿第一方向设置; 多个第二互连件，每个第二互连件沿第一方向设置; 以及沿着与第一方向不同的第三方向设置的多个第三互连。
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87.发明授权公开(公告)号：US09437296B2
公开(公告)日：2016-09-06
申请号：US14305371
申请日：2014-06-16
CPC分类号： H01L27/249 , G11C13/0002 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0069 , G11C2213/71 , H01L27/2454 , H01L45/085 , H01L45/1233 , H01L45/146
摘要： A semiconductor memory device according to an embodiment includes a memory cell array and a control circuit. The memory cell array includes: a plurality of first conductive layers that are stacked; a memory layer provided on a side surface of the plurality of the first conductive layers; and a second conductive layer that contacts the side surface of the plurality of the first conductive layers via the memory layer. A thickness of the first conductive layer disposed at the first position is larger than a thickness of the first conductive layer disposed at the second position. The control circuit is configured to apply a first voltage to a selected first conductive layer. The control circuit changes a value of the first voltage based on a position of the selected first conductive layer.
摘要翻译： 根据实施例的半导体存储器件包括存储单元阵列和控制电路。 存储单元阵列包括：堆叠的多个第一导电层; 存储层，设置在所述多个所述第一导电层的侧面上; 以及经由存储层与多个第一导电层的侧表面接触的第二导电层。 设置在第一位置处的第一导电层的厚度大于设置在第二位置的第一导电层的厚度。 控制电路被配置为对所选择的第一导电层施加第一电压。 控制电路基于所选择的第一导电层的位置来改变第一电压的值。
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公开(公告)号：US09425237B2
公开(公告)日：2016-08-23
申请号：US14588185
申请日：2014-12-31
申请人： Crossbar, Inc.
发明人： Sung Hyun Jo
CPC分类号： G11C13/0097 , G11C11/16 , G11C11/1659 , G11C11/56 , G11C13/0002 , G11C13/0007 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2213/15 , G11C2213/55 , G11C2213/71 , G11C2213/76 , G11C2213/77 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L27/249 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： Solid-state memory having a non-linear current-voltage (I-V) response is provided. By way of example, the solid-state memory can be a selector device. The selector device can be formed in series with a non-volatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the non-volatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.
摘要翻译： 提供具有非线性电流 - 电压（I-V）响应的固态存储器。 作为示例，固态存储器可以是选择器装置。 选择器装置可以通过单片制造工艺与非易失性存储器件串联形成。 此外，选择器装置可以提供适于缓解非易失性存储器件的泄漏电流的基本上非线性的I-V响应。 在各种公开的实施例中，选择器装置和非易失性存储装置的串联组合可以用作1-晶体管，多电阻电阻存储单元阵列中的一组存储单元。
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公开(公告)号：US20160232970A1
公开(公告)日：2016-08-11
申请号：US15131142
申请日：2016-04-18
发明人： Kenichi MUROOKA
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G06F3/0611 , G06F3/0659 , G06F3/0673 , G11C7/1006 , G11C13/0002 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C2213/71 , H01L27/2454 , H01L27/249 , H01L45/16
摘要： A memory device according to an embodiment comprises a data processing circuit that includes: a data write pre-processing circuit that processes input data to generate first intermediate data; a data write processing circuit that sequentially sets a voltage difference between a selected row line and a selected global bit line based on the first intermediate data; a data read processing circuit that detects a current flowing in the selected global bit line or a voltage of the selected global bit line and sequentially generates second intermediate data from a result of that detection; and a data read post-processing circuit that processes the second intermediate data to generate output data, the data write pre-processing circuit and the data read post-processing circuit having a correcting function that corrects a difference that may occur between the input data and the output data.
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公开(公告)号：US20160163733A1
公开(公告)日：2016-06-09
申请号：US15009040
申请日：2016-01-28
申请人： Jintaek Park , Youngwoo Park
发明人： Jintaek Park , Youngwoo Park
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , G11C5/02 , G11C5/063 , H01L27/249 , H01L45/10 , H01L45/1226 , H01L45/146 , H01L45/148
摘要： A three-dimensional semiconductor device includes bit lines provided on a substrate, a gate structure provided between the substrate and the bit lines, a common source line provided between the gate structure and the bit lines, and channel pipes connecting the bit lines to the common source line. Each of the channel pipes may include a pair of vertical portions extending through the gate structure and a horizontal portion connecting the vertical portions. The pair of vertical portions are provided under a pair of the bit lines arranged adjacent to each other, respectively.
摘要翻译： 三维半导体器件包括设置在衬底上的位线，设置在衬底和位线之间的栅极结构，设置在栅极结构和位线之间的公共源极线，以及将位线连接到公共端 源线。 每个通道管可以包括延伸穿过栅极结构的一对垂直部分和连接垂直部分的水平部分。 一对垂直部分分别设置在彼此相邻布置的一对位线下方。
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