公开(公告)号：US09257345B2

公开(公告)日：2016-02-09

申请号：US14638929

申请日：2015-03-04

Applicant: SK hynix Inc.

Inventor： Min Chul Sung

IPC: H01L23/52 ,  H01L21/8234 ,  H01L23/525 ,  H01L21/66 ,  H01L27/112 ,  H01L27/118

CPC classification number: H01L21/823475 ,  H01L22/22 ,  H01L23/5252 ,  H01L27/11206 ,  H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An anti-fuse array of a semiconductor device and a method for forming the same are disclosed. The anti-fuse array for a semiconductor device includes a first-type semiconductor substrate formed to define an active region by a device isolation region, a second-type impurity implantation region formed in the active region, a first-type channel region isolated from the semiconductor substrate by the second-type impurity implantation region, a gate electrode formed over the channel region, and a first metal contact formed over the second-type impurity implantation region.

公开(公告)号：US20160013199A1

公开(公告)日：2016-01-14

申请号：US14719342

申请日：2015-05-22

Applicant: eMemory Technology Inc.

Inventor： Te-Hsun Hsu ,  Chun-Hsiao Li ,  Hsuen-Wei Chen

IPC: H01L27/115

CPC classification number: G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C17/04 ,  G11C17/08 ,  G11C17/146 ,  G11C17/16 ,  G11C17/18 ,  G11C29/76 ,  H01L23/5252 ,  H01L23/528 ,  H01L27/0629 ,  H01L27/11206 ,  H01L27/11524 ,  H01L29/1079 ,  H01L29/4916 ,  H01L29/93 ,  H01L2924/0002 ,  H03K3/356182 ,  H01L2924/00

Abstract: A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor serially connected to the select transistor and disposed on the first OD region. The PMOS floating gate transistor includes a floating gate overlying the first OD region. A memory P well is disposed in the semiconductor substrate. A memory N well is disposed in the memory P well. The memory P well overlaps with the first OD region and the second OD region. The memory P well has a junction depth that is deeper than a trench depth of the isolation region. The memory N well has a junction depth that is shallower than the trench depth of the isolation region.

Abstract translation: 非易失性存储单元包括半导体衬底，第一OD区域，第二OD区域，将第一OD区域与第二OD区域分离的隔离区域，设置在第一OD区域上的PMOS选择晶体管和PMOS浮栅晶体管 串联连接到选择晶体管并且设置在第一OD区域上。 PMOS浮栅晶体管包括覆盖第一OD区的浮置栅极。 存储器P阱设置在半导体衬底中。 存储器N阱设置在存储器P中。 存储器P与第一OD区和第二OD区很好地重叠。 存储器P阱具有比隔离区域的沟槽深度更深的结深度。 存储器N阱具有比隔离区的沟槽深度浅的结深度。

公开(公告)号：US20150380102A1

公开(公告)日：2015-12-31

申请号：US14676819

申请日：2015-04-02

Applicant: Hyun-Min CHOI ,  Shigenobu MAEDA

Inventor： Hyun-Min CHOI ,  Shigenobu MAEDA

IPC: G11C17/16

CPC classification number: G11C17/16 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device includes first through fourth active regions arranged sequentially along a first direction, and which extend along a second direction different from the first direction; a first gate electrode formed on the first through fourth active regions to intersect the first through fourth active regions, and extending along the first direction; a second gate electrode formed on the first through fourth active regions to intersect the first through fourth active regions, extending along the second direction, and arranged so that no other gate electrodes are between the first gate electrode and the second gate electrode in the second direction; the first gate electrode extending between a first end and a second end;a first wiring line which is formed on the first gate electrode; a first strap contact, which connects the first wiring line and the first gate electrode between the first active region and the second active region; and a second strap contact, which connects the first wiring line and the first gate electrode between the third active region and the fourth active region.

Abstract translation: 存储器件包括沿着第一方向依次布置并沿着不同于第一方向的第二方向延伸的第一至第四有源区; 形成在所述第一至第四有源区上以与所述第一至第四有源区相交并沿所述第一方向延伸的第一栅电极; 形成在所述第一至第四有源区上以与所述第一至第四有源区相交的第二栅极，沿着所述第二方向延伸，并且被布置成使得在所述第一栅电极和所述第二栅电极之间在第二方向上不存在其它栅电极 ; 所述第一栅电极在第一端和第二端之间延伸; 形成在第一栅电极上的第一布线; 第一带接触件，其将所述第一布线和所述第一栅电极连接在所述第一有源区和所述第二有源区之间; 以及第二带接触件，其在第三有源区域和第四有源区域之间连接第一布线和第一栅电极。

公开(公告)号：US20150357680A1

公开(公告)日：2015-12-10

申请号：US14719831

申请日：2015-05-22

Applicant: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.

Inventor： Tobias Erlbacher ,  Vincent Lorentz ,  Reinhold Waller ,  Gudrun Rattmann

IPC: H01M10/42 ,  H01L29/45 ,  H01L23/532 ,  H01L23/525 ,  H01L29/36 ,  H01L29/861 ,  H01L29/06

CPC classification number: H01M10/425 ,  B60L3/0046 ,  B60L3/04 ,  B60L11/1879 ,  H01L23/5252 ,  H01L23/5256 ,  H01L23/53214 ,  H01L29/0684 ,  H01L29/0688 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/36 ,  H01L29/417 ,  H01L29/45 ,  H01L29/452 ,  H01L29/456 ,  H01L29/861 ,  H01L29/8611 ,  H01L2924/0002 ,  H01M2/348 ,  H01M10/4207 ,  H01M2200/103 ,  H01M2220/20 ,  H01M2220/30 ,  Y02T10/7005 ,  Y02T10/705 ,  H01L2924/00

Abstract: A semiconductor substrate has a first doping region arranged at a surface and a second doping region adjacent to the first doping region. A p-n junction between the doping regions is at least partially arranged less than 5 μm away from a contact area of the first doping region arranged at the substrate surface. A first contact structure is in contact with the first doping region in the contact area of the first doping region and has at least partially an electrically conductive material provided for a diffusion into the semiconductor substrate. The first contact structure is configured so that the conductive material provided for a diffusion into the substrate diffuses at least partially through the first doping region into the second doping region in case predefined trigger conditions occur. A second contact structure is in contact with the second doping region in a contact area of the second doping region.

Abstract translation: 半导体衬底具有布置在表面处的第一掺杂区域和与第一掺杂区域相邻的第二掺杂区域。 掺杂区域之间的p-n结至少部分地布置在距布置在衬底表面处的第一掺杂区域的接触面积小于5μm的位置。 第一接触结构与第一掺杂区域的接触区域中的第一掺杂区域接触，并且至少部分地具有用于扩散到半导体衬底中的导电材料。 第一接触结构被配置为使得设置用于扩散到衬底中的导电材料在发生预定义的触发条件的情况下至少部分地扩散通过第一掺杂区域进入第二掺杂区域。 第二接触结构在第二掺杂区域的接触区域中与第二掺杂区域接触。

公开(公告)号：US20150287732A1

公开(公告)日：2015-10-08

申请号：US14675758

申请日：2015-04-01

Applicant: eMemory Technology Inc.

Inventor： Mu-Ying Tsao ,  Wei-Ren Chen

IPC: H01L27/115

CPC classification number: G11C5/06 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L23/528 ,  H01L27/11206 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11558 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/7817 ,  H01L29/7835 ,  H01L29/93 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A nonvolatile memory (NVM) cell includes a semiconductor substrate having therein an N well and a P well; a first OD region and a second OD region disposed within the N well; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor serially connected to the select transistor and being disposed on the on the first OD region, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region; and an assistant gate protruding from one distal end of the floating gate to one edge of the second OD region such that the assistant gate is capacitively coupled to the second OD region and the N well. The select transistor, the floating gate transistor and the assistant gate disposed on the same N well.

Abstract translation: 非易失性存储器（NVM）单元包括其中具有N阱和P阱的半导体衬底; 设置在N阱内的第一OD区域和第二OD区域; 设置在所述第一OD区上的PMOS选择晶体管; 串联连接到所述选择晶体管并设置在所述第一OD区上的PMOS浮栅晶体管，其中所述PMOS浮栅晶体管包括覆盖所述第一OD区的浮置栅; 以及从所述浮动栅极的一个远端突出到所述第二OD区域的一个边缘的辅助栅极，使得所述辅助栅极电容耦合到所述第二OD区域和所述N阱。 选择晶体管，浮栅晶体管和辅助栅极位于相同的N阱上。

公开(公告)号：US09136153B2

公开(公告)日：2015-09-15

申请号：US13492395

申请日：2012-06-08

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Ze'ev Wurman ,  Paul Lim

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Ze'ev Wurman ,  Paul Lim

IPC: H01L25/00 ,  H01L25/065 ,  H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/115 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5252 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/16225 ,  H01L2924/00012

Abstract: A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and includes aluminum or copper; a second layer including second transistors; where the second transistors are aligned to the first transistors with a less than 40 nm alignment error, and where the second layer is overlying the first interconnection layer, and where at least one of the second transistors has a back-bias structure designed to modify the performance of at least one of the second transistors.

Abstract translation: 一种3D半导体器件，包括：包括第一晶体管的第一层; 互连第一晶体管并且包括铝或铜的第一互连层; 包括第二晶体管的第二层; 其中所述第二晶体管与所述第一晶体管对准，具有小于40nm的对准误差，并且其中所述第二层覆盖所述第一互连层，并且其中所述第二晶体管中的至少一个具有背偏置结构， 至少一个第二晶体管的性能。

公开(公告)号：US09123724B2

公开(公告)日：2015-09-01

申请号：US14134097

申请日：2013-12-19

Applicant: Intel Corporation

Inventor： Xianghong Tong ,  Zhanping Chen ,  Walid M. Hafez ,  Zhiyong Ma ,  Sarvesh H. Kulkarni ,  Kevin X. Zhang ,  Matthew B. Pedersen ,  Kevin D. Johnson

IPC: H01L27/11 ,  H01L29/04 ,  H01L21/02 ,  H01L23/58 ,  H01L23/525 ,  H01L27/02 ,  H01L27/112 ,  H01L27/06 ,  H01L21/44 ,  H01L29/861

CPC classification number: H01L23/5252 ,  H01L21/44 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/11206 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.

Abstract translation: 描述了形成和使用微电子结构的方法。 实施例包括在金属熔丝栅极和PMOS器件之间形成二极管，其中二极管设置在金属熔丝栅极的触点和PMOS器件的触点之间，并且其中二极管将金属熔丝栅极的触点耦合到 PMOS器件的接触。

公开(公告)号：US09117525B2

公开(公告)日：2015-08-25

申请号：US13785501

申请日：2013-03-05

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Satoshi Inoue

IPC: G11C11/34 ,  G11C16/04 ,  H01L29/788 ,  H01L29/66 ,  H01L27/115 ,  G11C29/50 ,  H01L23/525 ,  G11C29/04

CPC classification number: G11C16/0408 ,  G11C29/50004 ,  G11C2029/0403 ,  H01L23/5252 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell and a select gate transistor formed on a semiconductor substrate. The memory cell includes a first gate insulating film, a first charge storage layer, a first intergate insulating film, and a first control gate. The first gate insulating film, the first charge storage layer, the first intergate insulating film, and the first control gate are formed on the semiconductor substrate in order. The select gate transistor includes a second gate insulating film, a first gate electrode, a second intergate insulating film, and a second control gate. The second gate insulating film, the first gate electrode, the second intergate insulating film, and the second control gate are formed on the semiconductor substrate in order. The second intergate insulating film different first and second thicknesses.

Abstract translation: 根据一个实施例，非易失性半导体存储器件包括形成在半导体衬底上的存储单元和选择栅极晶体管。 存储单元包括第一栅极绝缘膜，第一电荷存储层，第一栅极绝缘膜和第一控制栅极。 第一栅极绝缘膜，第一电荷存储层，第一栅极绝缘膜和第一控制栅极依次形成在半导体衬底上。 选择栅极晶体管包括第二栅极绝缘膜，第一栅极电极，第二栅极间绝缘膜和第二控制栅极。 第二栅极绝缘膜，第一栅极电极，第二栅极间绝缘膜和第二控制栅极依次形成在半导体衬底上。 第二隔间绝缘膜具有不同的第一和第二厚度。

公开(公告)号：US20150221656A1

公开(公告)日：2015-08-06

申请号：US14686291

申请日：2015-04-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsiao-Lan Yang

IPC: H01L27/112 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/11206 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5252 ,  H01L27/101 ,  H01L27/115 ,  H01L29/66484 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse.

Abstract translation: 一种器件包括衬底，衬底表面处的隔离区域以及隔离区域顶表面上的半导体区域。 导电特征设置在隔离区的顶表面上，其中导电特征与半导体区相邻。 介电材料设置在导电特征和半导体区域之间。 电介质材料，导电特征和半导体区域形成反熔丝。

公开(公告)号：US20150206810A1

公开(公告)日：2015-07-23

申请号：US14159657

申请日：2014-01-21

Applicant: United Microelectronics Corp.

Inventor： Hsin-Ming Hou ,  Ji-Fu Kung

IPC: H01L21/66 ,  H01L25/00 ,  H01L23/538 ,  H01L25/07

CPC classification number: H01L22/32 ,  H01L22/14 ,  H01L22/34 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/5382 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/32145 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/1304 ,  H01L2924/1434 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2924/014

Abstract: A stacked semiconductor structure and a manufacturing method for the same are provided. The stacked semiconductor structure is provided, which comprises a first semiconductor substrate, a second semiconductor substrate, a dielectric layer, a trench, a via, and a conductive structure. The first semiconductor substrate comprises a first substrate portion and a first conductive layer on an active surface of the first substrate portion. The second semiconductor substrate comprises a second substrate portion and a second conductive layer on an active surface of the second substrate portion. The trench passes through the second substrate portion and exposing the second conductive layer. The via passes through the dielectric layer and exposes the first conductive layer. The conductive structure has an upper portion filling the trench and a lower portion filling the via. Opposing side surfaces of the upper portion are beyond opposing side surfaces of the lower portion.

Abstract translation: 提供一种叠层半导体结构及其制造方法。 提供了堆叠的半导体结构，其包括第一半导体衬底，第二半导体衬底，电介质层，沟槽，通孔和导电结构。 第一半导体衬底包括在第一衬底部分的有源表面上的第一衬底部分和第一导电层。 第二半导体衬底包括在第二衬底部分的有源表面上的第二衬底部分和第二导电层。 沟槽穿过第二衬底部分并暴露第二导电层。 通孔穿过介电层并暴露出第一导电层。 导电结构具有填充沟槽的上部和填充通孔的下部。 上部的相对侧面超过下部的相对侧面。