公开(公告)号：US10043663B2

公开(公告)日：2018-08-07

申请号：US15395805

申请日：2016-12-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng-Wei Cheng ,  David L. Rath ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Brent A. Wacaser

IPC: H01L29/00 ,  H01L21/02 ,  C30B23/02 ,  C30B25/18 ,  C30B25/04 ,  C30B23/04 ,  C30B29/40 ,  C30B29/52 ,  H01L29/66 ,  H01L29/04

Abstract: A heteroepitaxially grown structure includes a substrate and a mask including a high aspect ratio trench formed on the substrate. A cavity is formed in the substrate having a shape with one or more surfaces and including a resistive neck region at an opening to the trench. A heteroepitaxially grown material is formed on the substrate and includes a first region in or near the cavity and a second region outside the first region wherein the second region contains fewer defects than the first region.

公开(公告)号：US20180197961A1

公开(公告)日：2018-07-12

申请号：US15917484

申请日：2018-03-09

Applicant: International Business Machines Corporation

Inventor： Kevin K. Chan ,  Cheng-Wei Cheng ,  Jack Oon Chu ,  Yanning Sun ,  Jeng-Bang Yau

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/45 ,  H01L29/201 ,  H01L29/20 ,  H01L29/08 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/285 ,  H01L21/283

CPC classification number: H01L29/41783 ,  H01L21/02546 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/32051 ,  H01L21/32134 ,  H01L29/0847 ,  H01L29/20 ,  H01L29/201 ,  H01L29/452 ,  H01L29/665 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7835

Abstract: A field effect transistor is provided which includes a plurality of fins, at least a portion of a given fin including a respective source region, and a raised source disposed at least partially on the fins and including III-V material. The field effect transistor further includes a diffusion barrier disposed at least partially on the raised source and including transition metal bonded with silicon or germanium, and a gate stack capacitively coupled at least to the respective source regions of the fins.

公开(公告)号：US20180069376A1

公开(公告)日：2018-03-08

申请号：US15810629

申请日：2017-11-13

Applicant: International Business Machines Corporation

Inventor： Cheng-Wei Cheng ,  Effendi Leobandung ,  Ning Li ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC: H01S5/183 ,  H01L31/18 ,  H01L33/00 ,  H01S5/187 ,  H01S5/343 ,  H01L31/0232 ,  H01L31/0304 ,  H01L33/30 ,  H01L33/12 ,  H01L33/10 ,  H01L31/105

CPC classification number: H01S5/18377 ,  H01L31/02327 ,  H01L31/0304 ,  H01L31/105 ,  H01L31/1852 ,  H01L33/0012 ,  H01L33/0066 ,  H01L33/025 ,  H01L33/105 ,  H01L33/12 ,  H01L33/30 ,  H01S5/021 ,  H01S5/0218 ,  H01S5/0262 ,  H01S5/18361 ,  H01S5/187 ,  H01S5/3432 ,  H01S5/34366

Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1-y), where 0.8

公开(公告)号：US09773812B2

公开(公告)日：2017-09-26

申请号：US15402359

申请日：2017-01-10

Applicant: International Business Machines Corporation

Inventor： Cheng-Wei Cheng ,  Pouya Hashemi ,  Effendi Leobandung ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L27/092 ,  H01L29/161 ,  H01L29/20 ,  H01L29/04

CPC classification number: H01L27/1211 ,  H01L21/823821 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/161 ,  H01L29/20

Abstract: A structure includes an off-axis Si substrate with an overlying s-Si1−xGex layer and a BOX between the off-axis Si substrate and the s-Si1−xGex layer. The structure further includes pFET fins formed in the s-Si1−xGex layer and a trench formed through the s-Si1−xGex layer, the BOX and partially into the off-axis Si substrate. The trench contains a buffer layer in contact with the off-axis Si substrate, a first Group III-V layer disposed on the buffer layer, a semi-insulating Group III-V layer disposed on the first Group III-V layer and a second Group III-V layer disposed on the semi-insulating Group III-V layer, as well as nFET fins formed in the second Group III-V layer. The s-Si1−xGex layer has a value of x that results from a condensation process that merges an initial s-Si1−xGex layer with an initial underlying on-axis Si layer. A method to fabricate the structure is also disclosed.

公开(公告)号：US09726819B2

公开(公告)日：2017-08-08

申请号：US15363471

申请日：2016-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng-Wei Cheng ,  Ning Li ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC: H01L31/0232 ,  G02B6/12 ,  H01L31/173 ,  H04B10/80 ,  G02B6/122 ,  G02B6/13 ,  G02B6/132 ,  G02B6/136 ,  H01L27/12 ,  H01S5/026 ,  H01S5/30 ,  H01S5/343 ,  H01L31/18 ,  H01L33/00 ,  H01L33/50

CPC classification number: G02B6/12004 ,  G02B6/12002 ,  G02B6/1228 ,  G02B6/131 ,  G02B6/132 ,  G02B6/136 ,  G02B2006/12121 ,  G02B2006/12123 ,  H01L27/1203 ,  H01L31/0232 ,  H01L31/02322 ,  H01L31/173 ,  H01L31/1836 ,  H01L33/007 ,  H01L33/502 ,  H01S5/0261 ,  H01S5/0262 ,  H01S5/3013 ,  H01S5/343 ,  H02S40/44 ,  H04B10/801

Abstract: An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate. The interlevel dielectric layer is present over the first and second semiconductor devices. An optical interconnect is positioned over the second portion of the semiconductor substrate. At least one material layer of the optical interconnect includes an epitaxial material that is in direct contact with a seed surface within the second portion of the substrate through a via extending through the least one interlevel dielectric layer.

公开(公告)号：US20170092763A1

公开(公告)日：2017-03-30

申请号：US15377722

申请日：2016-12-13

Applicant: International Business Machines Corporation

Inventor： Cheng-Wei Cheng ,  Pranita Kerber ,  Effendi Leobandung ,  Amlan Majumdar ,  Renee T. Mo ,  Yanning Sun

IPC: H01L29/78 ,  H01L21/311 ,  H01L29/32 ,  H01L29/66 ,  H01L23/535 ,  H01L29/06

CPC classification number: H01L29/7835 ,  H01L21/2258 ,  H01L21/31105 ,  H01L21/31116 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/32 ,  H01L29/66462 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure containing a high mobility semiconductor channel material, i.e., a III-V semiconductor material, and asymmetrical source/drain regions located on the sidewalls of the high mobility semiconductor channel material is provided. The asymmetrical source/drain regions can aid in improving performance of the resultant device. The source region contains a source-side epitaxial doped semiconductor material, while the drain region contains a drain-side epitaxial doped semiconductor material and an underlying portion of the high mobility semiconductor channel material.

公开(公告)号：US20170092722A1

公开(公告)日：2017-03-30

申请号：US15135655

申请日：2016-04-22

Applicant: International Business Machines Corporation

Inventor： Kevin K. Chan ,  Cheng-Wei Cheng ,  Jack Oon Chu ,  Yanning Sun ,  Jeng-Bang Yau

IPC: H01L29/08 ,  H01L29/20 ,  H01L21/02 ,  H01L29/78 ,  H01L29/45 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/417 ,  H01L21/285

CPC classification number: H01L29/41783 ,  H01L21/02546 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/32051 ,  H01L21/32134 ,  H01L29/0847 ,  H01L29/20 ,  H01L29/201 ,  H01L29/452 ,  H01L29/665 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7835

Abstract: A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source comprising III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial layer comprising silicon or germanium. A metal layer is formed at least partially on the interfacial layer with the metal layer comprising transition metal. The diffusion barrier is formed at least partially on the raised source with the diffusion barrier layer comprising transition metal from the metal layer bonded to silicon or germanium from the interfacial layer. Similar processing forms a corresponding diffusion barrier on a raised drain.

公开(公告)号：US20170069491A1

公开(公告)日：2017-03-09

申请号：US14845346

申请日：2015-09-04

Applicant: international Business Machines Corporation

Inventor： Cheng-Wei Cheng ,  Ning Li ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC: H01L21/02 ,  H01L21/3065 ,  H01L21/285 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3205

CPC classification number: H01L21/3065 ,  H01L21/02293 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02538 ,  H01L21/2056 ,  H01L21/30612 ,  H01L21/7813

Abstract: A method comprises providing a sacrificial release layer on a base substrate; forming a device layer on the sacrificial release layer; depositing a metal stressor layer on the device layer; etching the sacrificial release layer; and using epitaxial lift off to release the device layer and the metal stressor layer from the base substrate.

Abstract translation: 一种方法包括在基底基板上提供牺牲剥离层; 在所述牺牲隔离层上形成器件层; 在器件层上沉积金属应力层; 蚀刻牺牲隔离层; 并且使用外延剥离来从基底衬底释放器件层和金属应力层。

公开(公告)号：US20170053796A1

公开(公告)日：2017-02-23

申请号：US15343078

申请日：2016-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng-Wei Cheng ,  Jeehwan Kim ,  John A. Ott ,  Devendra K. Sadana

IPC: H01L21/027 ,  H01L21/02

CPC classification number: H01L21/0274 ,  H01L21/02378 ,  H01L21/02444 ,  H01L21/02485 ,  H01L21/02527 ,  H01L21/0254 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/308

Abstract: A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material.

Abstract translation: 一种用于形成外延结构的方法包括在晶体半导体材料上提供二维材料并打开二维材料的部分以露出晶体半导体材料。 在晶体半导体材料中开放的部分中外延生长结构，使得外延生长对于暴露的晶体半导体材料相对于二维材料是选择性的。

公开(公告)号：US20160254352A1

公开(公告)日：2016-09-01

申请号：US15146148

申请日：2016-05-04

Applicant: International Business Machines Corporation

Inventor： Cheng-Wei Cheng ,  Pranita Kerber ,  Young-Hee Kim ,  Effendi Leobandung ,  Yanning Sun

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L29/207 ,  H01L29/08 ,  H01L21/02

CPC classification number: H01L29/20 ,  H01L21/02392 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/0257 ,  H01L21/30612 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/8252 ,  H01L29/0603 ,  H01L29/0607 ,  H01L29/0657 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1041 ,  H01L29/1054 ,  H01L29/12 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833

Abstract: A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant and epitaxially growing a source or drain on the halo layer using a second in-situ dopant, wherein the first in-situ dopant and the second in-situ dopant are of opposite doping polarity. Using an opposite doping polarity may provide an energy band barrier for the semiconductor device and reduce leakage current. A corresponding apparatus is also disclosed herein.