Invention Application
- Patent Title: III-V MOSFET WITH SELF-ALIGNED DIFFUSION BARRIER
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Application No.: US15135655Application Date: 2016-04-22
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Publication No.: US20170092722A1Publication Date: 2017-03-30
- Inventor: Kevin K. Chan , Cheng-Wei Cheng , Jack Oon Chu , Yanning Sun , Jeng-Bang Yau
- Applicant: International Business Machines Corporation
- Main IPC: H01L29/08
- IPC: H01L29/08 ; H01L29/20 ; H01L21/02 ; H01L29/78 ; H01L29/45 ; H01L21/3213 ; H01L29/66 ; H01L29/417 ; H01L21/285
Abstract:
A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source comprising III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial layer comprising silicon or germanium. A metal layer is formed at least partially on the interfacial layer with the metal layer comprising transition metal. The diffusion barrier is formed at least partially on the raised source with the diffusion barrier layer comprising transition metal from the metal layer bonded to silicon or germanium from the interfacial layer. Similar processing forms a corresponding diffusion barrier on a raised drain.
Public/Granted literature
- US09853109B2 III-V MOSFET with self-aligned diffusion barrier Public/Granted day:2017-12-26
Information query
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