公开(公告)号：US20120187576A1

公开(公告)日：2012-07-26

申请号：US13437533

申请日：2012-04-02

Applicant: Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu ,  Hung-Jung Tu ,  Ku-Feng Yang

Inventor： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu ,  Hung-Jung Tu ,  Ku-Feng Yang

IPC: H01L23/538 ,  H01L23/488

CPC classification number: H01L21/8221 ,  H01L21/76898 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05609 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13099 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  Y10S148/164 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/013

Abstract: A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die.

Abstract translation: 半导体结构包括第一裸片，其包括第一衬底和第一衬底上的第一焊盘，第二裸片，具有与第一表面相对的第一表面和第二表面，其中第二裸片堆叠在第一裸片上， 层，其具有在第二管芯的侧壁上的垂直部分，以及在第一管芯上延伸的水平部分。

公开(公告)号：US08154038B2

公开(公告)日：2012-04-10

申请号：US12166020

申请日：2008-07-01

Applicant: Chen-Hua Yu ,  Wen-Chih Chiou ,  Ding-Yuan Chen ,  Chia-Lin Yu

Inventor： Chen-Hua Yu ,  Wen-Chih Chiou ,  Ding-Yuan Chen ,  Chia-Lin Yu

IPC: H01L33/00

CPC classification number: H01L33/10 ,  H01L33/32

Abstract: A device structure includes a substrate; a group-III nitride layer over the substrate; a metal nitride layer over the group-III nitride layer; and a light-emitting layer over the metal nitride layer. The metal nitride layer acts as a reflector reflecting the light emitted by the light-emitting layer.

Abstract translation: 一种器件结构包括：衬底; 在衬底上的III族氮化物层; III族氮化物层上的金属氮化物层; 以及金属氮化物层上方的发光层。 金属氮化物层用作反射由发光层发射的光的反射器。

公开(公告)号：US20120074562A1

公开(公告)日：2012-03-29

申请号：US12890094

申请日：2010-09-24

Applicant: Chen-Hua Yu ,  Wen-Chih Chiou ,  Tsang-Jiuh Wu

Inventor： Chen-Hua Yu ,  Wen-Chih Chiou ,  Tsang-Jiuh Wu

IPC: H01L23/485 ,  H01L21/762

CPC classification number: H01L25/0657 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/53295 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06572

Abstract: A device includes an interposer free from active devices therein. The interposer includes a substrate; a through-substrate via (TSV) penetrating through the substrate; and a low-k dielectric layer over the substrate.

Abstract translation: 一种器件包括其中没有有源器件的插入器。 插入件包括基板; 贯穿基板的贯穿基板通孔（TSV）; 以及在该衬底上的低k电介质层。

公开(公告)号：US20120018876A1

公开(公告)日：2012-01-26

申请号：US12840949

申请日：2010-07-21

Applicant: Weng-Jin Wu ,  Ying-Ching Shih ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Weng-Jin Wu ,  Ying-Ching Shih ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/485 ,  H01L21/768

CPC classification number: H01L21/768 ,  H01L21/56 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/5384 ,  H01L24/11 ,  H01L24/14 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/81895 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/81805

Abstract: A device includes a first die having a first side and a second side opposite to first side, the first side includes a first region and a second region, and a first metal bump of a first horizontal size formed on the first region of the first side of the first die. A second die is bonded to the first side of the first die through the first metal bump. A dielectric layer is formed over the first side of the first die and includes a first portion directly over the second die, a second portion encircling the second die, and an opening exposing the second region of the first side of the first die. A second metal bump of a second horizontal size is formed on the second region of the first side of the first die and extending into the opening of the dielectric layer. The second horizontal size is greater than the first horizontal size. An electrical component is bonded to the first side of the first die through the second metal bump.

Abstract translation: 一种器件包括具有第一侧和与第一侧相对的第二侧的第一管芯，第一侧包括第一区域和第二区域，以及形成在第一侧面的第一区域上的第一水平尺寸的第一金属凸块 的第一个死亡。 通过第一金属凸块将第二模具结合到第一模具的第一侧。 介电层形成在第一管芯的第一侧上，并且包括直接在第二管芯上方的第一部分，环绕第二管芯的第二部分和暴露第一管芯的第一侧的第二区域的开口。 第二水平尺寸的第二金属凸块形成在第一模具的第一侧的第二区域上并且延伸到电介质层的开口中。 第二个水平尺寸大于第一个水平尺寸。 电子部件通过第二金属凸块接合到第一管芯的第一侧。

公开(公告)号：US20120007048A1

公开(公告)日：2012-01-12

申请号：US13237181

申请日：2011-09-20

Applicant: Chia-Lin Yu ,  Ding-Yuan Chen ,  Chen-Hua Yu ,  Wen-Chih Chiou

Inventor： Chia-Lin Yu ,  Ding-Yuan Chen ,  Chen-Hua Yu ,  Wen-Chih Chiou

IPC: H01L29/12 ,  H01L21/20

CPC classification number: H01L33/04 ,  H01L33/12 ,  H01L33/32

Abstract: A semiconductor structure includes a substrate and a conductive carrier-tunneling layer over and contacting the substrate. The conductive carrier-tunneling layer includes first group-III nitride (III-nitride) layers having a first bandgap, wherein the first III-nitride layers have a thickness less than about 5 nm; and second III-nitride layers having a second bandgap lower than the first bandgap, wherein the first III-nitride layers and the second III-nitride layers are stacked in an alternating pattern. The semiconductor structure is free from a III-nitride layer between the substrate and the conductive carrier-tunneling layer. The semiconductor structure further includes an active layer over the conductive carrier-tunneling layer.

Abstract translation: 半导体结构包括衬底和与衬底接触的导电载体隧穿层。 导电载体隧穿层包括具有第一带隙的第一III族氮化物（III族氮化物）层，其中第一III族氮化物层具有小于约5nm的厚度; 和具有比第一带隙低的第二带隙的第二III族氮化物层，其中第一III族氮化物层和第二III族氮化物层以交替图案堆叠。 半导体结构在衬底和导电载体 - 隧穿层之间不含III族氮化物层。 半导体结构还包括在导电载体 - 隧穿层上的有源层。

公开(公告)号：US20110277655A1

公开(公告)日：2011-11-17

申请号：US12778867

申请日：2010-05-12

Applicant: Francis Ko ,  Chi-Chun Hsieh ,  Shang-Yun Hou ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Francis Ko ,  Chi-Chun Hsieh ,  Shang-Yun Hou ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: B41F33/00

CPC classification number: H01L23/5384 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49883 ,  H01L23/525 ,  H01L23/5328 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13009 ,  H01L2224/13147 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method of forming a device includes printing conductive patterns on a dielectric sheet to form a pre-ink-printed sheet, and bonding the pre-ink-printed sheet onto a side of a substrate. The conductive feature includes a through-substrate via extending from a first major side of the substrate to a second major side of the substrate opposite the first major side. A conductive paste is then applied to electrically couple conductive patterns to a conductive feature in the substrate.

Abstract translation: 形成器件的方法包括在电介质片上印刷导电图案以形成预先印墨的片材，以及将预印墨片材粘合到基片的一侧上。 导电特征包括从衬底的第一主侧延伸到与第一主侧相对的衬底的第二主侧的贯通衬底。 然后施加导电膏以将导电图案电耦合到衬底中的导电特征。

公开(公告)号：US08053900B2

公开(公告)日：2011-11-08

申请号：US12255060

申请日：2008-10-21

Applicant: Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

Inventor： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

IPC: H01L23/48

CPC classification number: H01L24/05 ,  H01L24/06 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/16106 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/81894 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/12 ,  H01L2224/05552

Abstract: An integrated circuit structure includes a semiconductor chip, which further includes a first surface; and a patterned bond pad exposed through the first surface. The patterned bond pad includes a plurality of portions electrically connected to each other, and at least one opening therein. The integrated circuit further includes a dielectric material filled into at least a portion of the at least one opening.

Abstract translation: 集成电路结构包括还包括第一表面的半导体芯片; 以及通过第一表面暴露的图案化接合焊盘。 图案化接合焊盘包括彼此电连接的多个部分和其中的至少一个开口。 集成电路还包括填充到至少一个开口的至少一部分中的电介质材料。

公开(公告)号：US07879711B2

公开(公告)日：2011-02-01

申请号：US11563973

申请日：2006-11-28

Applicant: Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu ,  Jean Wang

Inventor： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu ,  Jean Wang

IPC: H01L21/44

CPC classification number: H01L21/76898 ,  H01L23/3114 ,  H01L23/3185 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/08145 ,  H01L2224/13009 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13025 ,  H01L2224/14051 ,  H01L2224/14135 ,  H01L2224/14155 ,  H01L2224/14179 ,  H01L2224/17517 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29035 ,  H01L2224/29075 ,  H01L2224/29116 ,  H01L2224/29124 ,  H01L2224/29147 ,  H01L2224/29169 ,  H01L2224/29184 ,  H01L2224/29186 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81193 ,  H01L2224/83193 ,  H01L2224/9202 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12041 ,  H01L2924/14 ,  Y10S438/926 ,  H01L2924/00 ,  H01L2924/053 ,  H01L2924/049 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A method includes: forming a transistor gate over a first substrate and at least one first dummy structure within the first substrate; forming an interlayer dielectric (ILD) layer over the gate transistor, the ILD layer including at least one contact structure formed therein and making electrical contact with the transistor gate and at least one first conductive structure formed therethrough at least partially over a surface of the dummy structure; forming a passivation layer over the ILD layer, the passivation layer comprising at least one first pad structure formed therein and making electrical contact with the conductive structure; bonding the first substrate with a second substrate; removing at least a portion of the first dummy structure, thereby forming a first opening; and forming a conductive material within the first opening for formation of a second conductive structure, the second conductive structure being electrically coupled to the first conductive structure.

Abstract translation: 一种方法包括：在第一衬底和第一衬底内的至少一个第一虚拟结构之上形成晶体管栅极; 在所述栅极晶体管上形成层间电介质层（ILD）层，所述ILD层包括形成在其中的至少一个接触结构，并与所述晶体管栅极形成电接触;以及至少一个第一导电结构，其至少部分地形成在所述虚拟 结构体; 在所述ILD层上形成钝化层，所述钝化层包括形成在其中并与所述导电结构电接触的至少一个第一焊盘结构; 用第二衬底接合第一衬底; 去除所述第一虚设结构的至少一部分，从而形成第一开口; 以及在所述第一开口内形成导电材料以形成第二导电结构，所述第二导电结构电耦合到所述第一导电结构。

公开(公告)号：US07872357B2

公开(公告)日：2011-01-18

申请号：US12043023

申请日：2008-03-05

Applicant: Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

Inventor： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/3171 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/81054 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/8192 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/01039 ,  H01L2924/00

Abstract: The formation of bonding pad protective layer over exposed bonding pad materials between stacked integrated circuit (IC) dies or wafers is described in preferred embodiments in which the bonding pad protective layer is formed in the integrated process of forming wafer bonding pads. The bonding pad protective layer prevents the exposed bonding pad materials from oxidation and corrosion in open-air or other harsh environments. By providing a bonding pad protective layer on exposed bonding pad materials, significant product reliability improvement is expected on ICs having a three-dimensional “stacked-die” configuration.

Abstract translation: 在堆叠的集成电路（IC）晶片之间的暴露的焊盘材料上的焊盘保护层的形成在其中在形成晶片接合焊盘的集成工艺中形成焊盘保护层的优选实施例中进行了描述。 接合焊盘保护层防止暴露的焊盘材料在露天或其他恶劣环境中受到氧化和腐蚀。 通过在暴露的焊盘材料上提供焊盘保护层，预期在具有三维“堆叠 - 裸片”结构的IC上可以显着提高产品的可靠性。

公开(公告)号：US20110006428A1

公开(公告)日：2011-01-13

申请号：US12617900

申请日：2009-11-13

Applicant: Ching-Yu Lo ,  Hung-Jung Tu ,  Hai-Ching Chen ,  Tien-I Bao ,  Wen-Chih Chiou ,  Chen-Hua Yu

Inventor： Ching-Yu Lo ,  Hung-Jung Tu ,  Hai-Ching Chen ,  Tien-I Bao ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L23/48

CPC classification number: H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L2221/68372 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner.

Abstract translation: 集成电路结构包括半导体衬底; 贯穿半导体衬底的贯通半导体通孔（TSV）开口; 和TSV开口的TSV衬管。 TSV衬套包括在TSV开口的侧壁上的侧壁部分和TSV开口底部的底部。 TSV衬管的底部部分的底部高度大于TSV衬套的侧壁部分的中间厚度。