公开(公告)号：US20160358872A1

公开(公告)日：2016-12-08

申请号：US15240291

申请日：2016-08-18

申请人： CHIPMOS TECHNOLOGIES INC.

发明人： TUNG BAO LU ,  HENG-SHENG WANG ,  TZU-HAN HSU

IPC分类号： H01L23/00 ,  H01L21/324

CPC分类号： H01L24/11 ,  C23C18/1653 ,  C25D3/60 ,  C25D3/62 ,  C25D5/02 ,  C25D5/505 ,  C25D7/123 ,  G02F1/1333 ,  H01L21/324 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/742 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L33/62 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/06102 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/00015 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/2064 ,  H01L2924/351 ,  H01L2924/0105 ,  H01L2224/48 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2224/81411 ,  H01L2924/0665

摘要： A semiconductor package comprises a semiconductor chip having an active surface with a conductive pad thereon; an electroplated Au—Sn. alloy bump over the active surface; and a (glass) substrate comprising conductive traces electrically coupling, with the electroplated Au—Sn alloy bump, wherein the electroplated Au—Sn alloy bump has a composition from about Au0.35Sn0.15 to about Au0.75Sn0.25 in weight percent uniformly distributed from an end in proximity to the active surface to an end in proximity to the substrate. A method of manufacturing a semiconductor package comprises forming patterns of conductive pads on an active surface of a semiconductor chip; electroplating Au—Sn alloy bump over the conductive pads; and bonding the semiconductor chip on a corresponding conductive trace on a substrate by reflow operation or a thermal press operation.

摘要翻译： 半导体封装包括其上具有导电焊盘的活性表面的半导体芯片; 电镀Au-Sn。 合金凸块在活性表面上; 和包含与电镀的Au-Sn合金凸块电连接的导电迹线的（玻璃）衬底，其中电镀的Au-Sn合金凸块的组成以重量百分比的均匀重量百分比约为Au0.35Sn0.15至约Au0.75Sn0.25 从靠近有源表面的端部分散到靠近基板的端部。 制造半导体封装的方法包括在半导体芯片的有源表面上形成导电焊盘的图案; 在导电焊盘上电镀Au-Sn合金凸块; 以及通过回流操作或热压操作将半导体芯片接合在基板上的相应导电迹线上。

公开(公告)号：US20160329269A1

公开(公告)日：2016-11-10

申请号：US14874486

申请日：2015-10-05

申请人： ChipMOS Technologies Inc. ,  ChipMOS Technologies (Bermuda) Ltd.

发明人： Chi-Jin Shih

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L23/49548 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49582 ,  H01L24/00 ,  H01L2021/60022 ,  H01L2224/16245 ,  H01L2924/181 ,  H01L2924/00012

摘要： A chip package structure including a lead frame, a chip, a plurality of solder bumps, a solder resist layer and an encapsulant is provided. The lead frame has a plurality of inner leads. Each of the inner leads has an upper surface, a lower surface, two side surfaces opposite to each other and a bonding area on the upper surface. The chip is disposed on the lead frame and has an active surface. Each of the solder bumps connects the active surface and the bonding area of each of the inner leads. The solder resist layer is disposed on at least one of the lower surface or the two side surfaces of each of the inner leads. The encapsulant covers the lead frame, the chip, the solder bumps and the solder resist layer. A manufacturing method of the chip package structure is also provided.

摘要翻译： 提供了包括引线框架，芯片，多个焊料凸块，阻焊层和密封剂的芯片封装结构。 引线框架具有多个内引线。 每个内引线具有上表面，下表面，彼此相对的两个侧表面和上表面上的接合区域。 芯片设置在引线框架上并具有有源表面。 每个焊料凸点连接每个内引线的有源表面和接合区域。 阻焊层设置在每个内引线的下表面或两个侧表面中的至少一个上。 密封剂覆盖引线框架，芯片，焊料凸块和阻焊层。 还提供了芯片封装结构的制造方法。

公开(公告)号：US20160315067A1

公开(公告)日：2016-10-27

申请号：US14855397

申请日：2015-09-16

申请人： ChipMOS Technologies Inc. ,  ChipMOS Technologies (Bermuda) Ltd.

发明人： Shih-Wen Chou

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3142 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14179 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83385 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2224/83

摘要： A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.

摘要翻译： 多芯片封装结构包括第一芯片，至少一个阻挡结构，多个第一导电凸块，第二芯片，多个第二导电凸块和底部填充。 第一芯片具有芯片连接区域，芯片连接区域中的多个第一内部焊盘和芯片连接区域外部的多个第一外部焊盘。 阻挡结构设置在第一内垫和第一外垫之间并且包围第一内垫。 第一导电凸块设置在第一外垫上。 第二芯片在芯片连接区域上翻转并具有多个第二焊盘。 第二导电凸块设置在第一内垫和第二垫之间。 底部填充物设置在第一芯片和第二芯片之间，以覆盖第二导电凸块。

公开(公告)号：US20160281257A1

公开(公告)日：2016-09-29

申请号：US14856485

申请日：2015-09-16

申请人： CHIPMOS TECHNOLOGIES INC

发明人： MING-CHENG LIN

IPC分类号： C25D17/00 ,  C25D17/02

CPC分类号： C25D17/008 ,  C25D17/001 ,  C25D17/06 ,  C25D17/10

摘要： An electrochemical reactor includes an adjustable electric field shaping capability during electroplating. The electrochemical reactor includes a reservoir configured to retain an electrolytic solution; a cathode and an anode disposed in the reservoir to form electric field lines passing through the electrolytic solution. Either the cathode or the anode includes a workpiece holder. A shield attaches to the cathode or the anode without the workpiece holder. The shield includes a surface configured to block a portion of the electric field lines, and a conduit positioned on the surface and configured to concentrate the electric field lines within the conduit. The conduit includes a protruding portion including a height measured from the surface to a top surface of the conduit, and an aperture penetrating the protruding portion and passing through the surface. The aperture is configured to allow the electric field lines to pass through the conduit.

摘要翻译： 电化学反应器包括电镀期间可调电场整形能力。 电化学反应器包括构造成保持电解液的储存器; 设置在储存器中的阴极和阳极，以形成通过电解液的电场线。 阴极或阳极都包括工件保持器。 屏蔽件连接到阴极或阳极而没有工件夹持器。 屏蔽包括被配置为阻挡电场线的一部分的表面，以及定位在表面上并被配置为将电场线集中在导管内的导管。 所述导管包括突出部分，所述突出部分包括从所述导管的表面到所述顶表面测量的高度，以及穿过所述突出部分并穿过所述表面的孔。 孔被配置成允许电场线通过导管。

公开(公告)号：US09437542B2

公开(公告)日：2016-09-06

申请号：US14985423

申请日：2015-12-31

申请人： ChipMOS Technologies Inc.

发明人： Tsung-Jen Liao

IPC分类号： H01L23/522 ,  H01L23/31 ,  H01L23/433 ,  H01L23/538 ,  H01L23/64 ,  H01L23/367 ,  H01L23/528 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L23/5227 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5389 ,  H01L23/645 ,  H01L24/06 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05025 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/18 ,  H01L2924/0002 ,  H01L2924/19042 ,  H01L2924/00

摘要： A chip package structure is provided. The chip package structure includes a chip, at least one inducting coil, a molding compound and a redistribution circuit layer. The chip includes an active surface, a back surface opposite to the active surface. The inducting coil is disposed around a periphery region of the chip. The molding compound covers the chip and the periphery region and exposes the active surface. The inducting coil is disposed at the molding compound. The redistribution circuit layer covers the active surface, part of the molding compound and part of the inducting coil, and electrically connects the chip.

公开(公告)号：US20150347806A1

公开(公告)日：2015-12-03

申请号：US14477870

申请日：2014-09-05

申请人： ChipMOS Technologies Inc. ,  ChipMOS Technologies (Bermuda) Ltd.

发明人： Li-Chun Li ,  Chia-I Tsai

IPC分类号： G06K9/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L24/81 ,  G06K9/00013 ,  H01L21/563 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81207 ,  H01L2224/83851 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/07025 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/1579 ,  H01L2924/00 ,  H01L2224/13099

摘要： A chip package structure includes a flexible substrate, a patterned circuit layer, a fingerprint sensor chip, a plurality of bumps, a patterned dielectric layer and an encapsulant layer. The patterned circuit layer disposed on the flexible substrate includes a fingerprint sensing circuit and a plurality of terminals. The fingerprint sensor chip disposed on the flexible substrate is electrically connected to the fingerprint sensing circuit and includes an active surface, a back surface, and a plurality of bonding pads disposed on the active surface. The bumps disposed between the fingerprint sensor chip and the patterned circuit layer electrically connect the bonding pads and the terminals. The patterned dielectric layer including a first surface and a second surface having a fingerprint sensing region at least covers the fingerprint sensing circuit with the first surface. The encapsulant layer is filled between the flexible substrate and the fingerprint sensor chip and covers the bumps.

摘要翻译： 芯片封装结构包括柔性衬底，图案化电路层，指纹传感器芯片，多个凸块，图案化电介质层和密封剂层。 设置在柔性基板上的图案化电路层包括指纹感测电路和多个端子。 设置在柔性基板上的指纹传感器芯片电连接到指纹感测电路，并且包括有源表面，后表面和设置在有源表面上的多个接合焊盘。 布置在指纹传感器芯片和图案化电路层之间的凸起电连接接合焊盘和端子。 包括具有指纹感测区域的第一表面和第二表面的图案化电介质层至少覆盖具有第一表面的指纹感测电路。 密封剂层填充在柔性基板和指纹传感器芯片之间并覆盖凸块。

公开(公告)号：US09123684B2

公开(公告)日：2015-09-01

申请号：US14304975

申请日：2014-06-15

申请人： ChipMOS Technologies Inc.

发明人： Tsung-Jen Liao

IPC分类号： H01L23/34 ,  H01L23/04 ,  H01L23/10 ,  H01L23/13 ,  H01L23/14 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L23/29 ,  H01L23/367

CPC分类号： H01L23/34 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/6836 ,  H01L23/13 ,  H01L23/142 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49568 ,  H01L24/48 ,  H01L24/82 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package structure including a leadframe, a chip, at least one heat dissipation pillar, and a molding compound is provided. The leadframe includes a die pad and a plurality of leads. The die pad has at least one through hole. The leads surround the die pad. The chip is located on the die pad and electronically connected to the leads. The chip includes an active surface and a back surface opposite to the active surface. The back surface of the chip is adhered to the die pad. The heat dissipation pillar is located on the back surface and passes through the through hole. The molding compound encapsulates the chip, at least parts of the leads, and the die pad. The molding compound includes at least one opening to expose the heat dissipation pillar. A manufacturing method of the chip package structure is also provided.

摘要翻译： 提供了包括引线框，芯片，至少一个散热柱和模塑料的芯片封装结构。 引线框架包括管芯焊盘和多个引线。 管芯焊盘至少有一个通孔。 引线围绕芯片焊盘。 芯片位于芯片焊盘上，并与引线电连接。 芯片包括有源表面和与有源表面相对的后表面。 芯片的背面粘附到芯片焊盘。 散热柱位于后表面，通过通孔。 模塑料封装芯片，引线的至少部分和芯片焊盘。 模塑料包括至少一个露出散热柱的开口。 还提供了芯片封装结构的制造方法。

公开(公告)号：US09053968B2

公开(公告)日：2015-06-09

申请号：US13655434

申请日：2012-10-18

申请人： ChipMOS Technologies Inc.

发明人： Shih-Wen Chou

IPC分类号： H01L23/495 ,  H01L25/10 ,  H01L23/13 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L25/105 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3121 ,  H01L2224/16225 ,  H01L2225/1029 ,  H01L2225/1088 ,  H01L2924/00014

摘要： A method of manufacturing a semiconductor package structure is provided. A supporting plate and multiple padding patterns on an upper surface of the supporting plate define a containing cavity. Multiple leads electrically insulated from one another are formed on the padding patterns, extend from top surfaces of the padding patterns along side surfaces to the upper surface and are located inside the containing cavity. A chip is mounted inside the containing cavity, electrically connected to the leads. A molding compound is formed to encapsulate at least the chip, a portion of the leads and a portion of the supporting plate, fill the containing cavity and gaps among the padding patterns, and exposes a portion of the leads on the top surface. The supporting plate is removed to expose a back surface of each padding pattern, a bottom surface of the molding compound and a lower surface of each lead.

摘要翻译： 提供一种制造半导体封装结构的方法。 支撑板的上表面上的支撑板和多个衬垫图案限定容纳腔。 在填充图案上形成彼此电绝缘的多个引线，从衬垫图案的顶表面沿着侧表面延伸到上表面并位于容纳腔内。 芯片安装在容纳腔内，电连接到引线。 形成模塑料以至少封装芯片，引线的一部分和支撑板的一部分填充填充图案中的容纳腔和间隙，并且使顶部表面上的一部分引线露出。 移除支撑板以暴露每个填充图案的背面，模制化合物的底表面和每个引线的下表面。

公开(公告)号：US08962395B2

公开(公告)日：2015-02-24

申请号：US13918518

申请日：2013-06-14

申请人： ChipMOS Technologies Inc.

发明人： Geng-Shin Shen

IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/495

CPC分类号： H01L24/11 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49551 ,  H01L23/49861 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/16245 ,  H01L2224/8191 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00012

摘要： The present invention provides a Quad Flat Non-leaded (QFN) package, which comprises a chip, a lead frame, a plurality of composite bumps and an encapsulant. The chip has a plurality of pads, and the lead frame has a plurality of leads. Each of the plurality of composite bumps has a first conductive layer and a second conductive layer. The first conductive layer is electrically connected between one of the pads and the second conductive layer, and the second conductive layer is electrically connected between the first conductive layer and one of the leads. The encapsulant encapsulates the chip, the leads and the composite bumps. Thereby, a QFN package with composite bumps and a semi-cured encapsulant is forming between the spaces of leads of lead frame before chip bonded to the lead frame are provided.

摘要翻译： 本发明提供一种四平坦无铅（QFN）封装，其包括芯片，引线框架，多个复合凸块和密封剂。 芯片具有多个焊盘，引线框架具有多个引线。 多个复合凸块中的每一个具有第一导电层和第二导电层。 第一导电层电连接在一个焊盘和第二导电层之间，并且第二导电层电连接在第一导电层和引线之一之间。 密封剂封装芯片，引线和复合凸块。 由此，在提供芯片接合到引线框架之前，在引线框架的引线的间隙之间形成具有复合凸块和半固化密封剂的QFN封装。

公开(公告)号：US08779604B1

公开(公告)日：2014-07-15

申请号：US14073040

申请日：2013-11-06

申请人： Chipmos Technologies Inc.

发明人： Shih Jye Cheng ,  Tung Bao Lu

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L23/485 ,  H01L23/498

CPC分类号： H01L21/4825 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/4985 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05027 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05541 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/11848 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/8159 ,  H01L2224/8169 ,  H01L2224/81744 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2224/81862 ,  H01L2224/83104 ,  H01L2924/01322 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/0655 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/1146

摘要： A semiconductor structure includes a device, a conductive pad on the device, and a Ag1-xYx alloy bump over the conductive pad. The Y of the Ag1-xYx bump comprises metals forming complete solid solution with Ag at arbitrary weight percentage, and the X of the Ag1-xYx alloy bump is in a range of from about 0.005 to about 0.25. A difference between one standard deviation and a mean value of a grain size distribution of the Ag1-xYx alloy bump is in a range of from about 0.2 μm to about 0.4 μm. An average grain size of the Ag1-xYx alloy bump on a longitudinal cross sectional plane is in a range of from about 0.5 μm to about 1.5 μm.

摘要翻译： 半导体结构包括器件，器件上的导电焊盘和导电焊盘上的Ag1-xYx合金凸块。 Ag1-xYx凸块的Y包括以任意重量百分比与Ag形成完全固溶体的金属，Ag1-xYx合金凸块的X在约0.005至约0.25的范围内。 Ag1-xYx合金凸块的一个标准偏差和晶粒度分布的平均值之间的差异在约0.2μm至约0.4μm的范围内。 Ag1-xYx合金凸块在纵截面上的平均粒径在约0.5μm至约1.5μm的范围内。