公开(公告)号：US08932960B2

公开(公告)日：2015-01-13

申请号：US13777803

申请日：2013-02-26

Applicant: Micron Technology, Inc.

Inventor： Luan C. Tran

IPC: H01L21/302 ,  H01L21/461 ,  H01L29/66 ,  H01L21/033 ,  H01L27/115 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L21/76816 ,  H01L21/02518 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28273 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0705 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11546 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/66477 ,  H01L29/66825 ,  H01L29/788

Abstract: Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other.

Abstract translation: 半导体材料的连续环路的不同部分彼此电隔离。 在一些实施例中，环路的端部与环路的中间部分电隔离。 在一些实施例中，具有在其端部连接在一起的两个腿的半导体材料的环通过间距倍增过程形成，其中间隔物的环形成在心轴的侧壁上。 去除心轴并且将一块掩模材料覆盖在间隔环的至少一端上。 在一些实施例中，掩模材料块覆盖间隔环的每一端。 由间隔物和块限定的图案被转移到半导体材料层。 这些块将所有环路电连接在一起。 沿循环的每条腿形成选择门。 这些块作为源/排水沟。 选择门被偏置在关闭状态以防止电流从环路的中部流向块，从而将中间部分与环的端部电隔离，并且还将环路的不同的腿与每个 其他。

公开(公告)号：US08928067B2

公开(公告)日：2015-01-06

申请号：US14054152

申请日：2013-10-15

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/02518 ,  H01L21/02636 ,  H01L21/265 ,  H01L29/66477 ,  H01L29/6681 ,  H01L29/785

Abstract: A computer program storage product includes instructions for forming a fin field-effect-transistor. The instructions are configured to perform a method. The method includes implanting a dopant into an exposed portion of a semiconductor substrate within a cavity. The cavity is formed in a dielectric layer on the semiconductor substrate. The cavity exposes the portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate. A height of the cavity defines a height of the epitaxially grown semiconductor.

Abstract translation: 计算机程序存储产品包括用于形成鳍状场效应晶体管的指令。 指令被配置为执行一种方法。 该方法包括将掺杂剂注入腔内的半导体衬底的暴露部分。 空腔形成在半导体衬底上的电介质层中。 空腔将半导体衬底的部分暴露在空腔内。 在半导体衬底的掺杂剂注入的暴露部分的顶部的腔内外延生长半导体层。 空腔的高度限定外延生长的半导体的高度。

公开(公告)号：US08900958B2

公开(公告)日：2014-12-02

申请号：US13719826

申请日：2012-12-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Meng-Yueh Liu

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/772 ,  H01L21/02 ,  H01L29/68

CPC classification number: H01L27/088 ,  H01L21/02518 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66636 ,  H01L29/68 ,  H01L29/7835 ,  H01L29/7848

Abstract: The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) descried enable forming an epitaxially grown silicon-containing material without using GeH4 in an etch gas mixture of an etch process for a cyclic deposition/etch (CDE) process. The etch process is performed at a temperature different form the deposition process to make the etch gas more efficient. As a result, the etch time is reduced and the throughput is increased.

Abstract translation: 用于形成描述的场效应晶体管（FET）的源极/漏极（S / D）区域的机构的实施例使得能够在用于循环沉积/蚀刻的蚀刻工艺的蚀刻气体混合物中形成外延生长的含硅材料，而不使用GeH 4 （CDE）过程。 蚀刻工艺在不同于沉积工艺的温度下进行，以使蚀刻气体更有效率。 结果，蚀刻时间减少并且生产量增加。

公开(公告)号：US20140332850A1

公开(公告)日：2014-11-13

申请号：US14447081

申请日：2014-07-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ji-Soo Park

IPC: C30B25/04 ,  H01L21/02 ,  C30B29/40 ,  H01L29/06 ,  C30B25/18 ,  C30B29/08

CPC classification number: C30B25/186 ,  C30B25/04 ,  C30B29/08 ,  C30B29/40 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02518 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/0684 ,  H01L29/165 ,  H01L29/34

Abstract: A device includes an epitaxially grown crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters which result in the dominant growth component of the crystal to be supplied laterally from side walls of the insulator. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.

Abstract translation: 一种器件包括在由绝缘体限制的区域内的外延生长的晶体材料。 结晶材料的表面具有减小的粗糙度。 一个实例包括通过产生导致晶体的主要生长成分从绝缘体的侧壁横向供应的工艺参数来获得具有减小的粗糙度的表面。 在优选实施例中，由绝缘体限制的区域是具有足以使用ART技术捕获缺陷的纵横比的绝缘体中的开口。

公开(公告)号：US20140206178A1

公开(公告)日：2014-07-24

申请号：US14129594

申请日：2012-07-13

Applicant: Yuri Georgievich Shreter ,  Yuri Toomasovich Rebane ,  Aleksey Vladimirovich Mironov

Inventor： Yuri Georgievich Shreter ,  Yuri Toomasovich Rebane ,  Aleksey Vladimirovich Mironov

IPC: H01L21/02

CPC classification number: H01L21/6835 ,  H01L21/02518 ,  H01L21/02527 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/02551 ,  H01L21/0257 ,  H01L21/02634 ,  H01L21/268 ,  H01L21/76254 ,  H01L33/0079 ,  H01L2221/68381

Abstract: The present invention proposes variations of the laser separation method allowing separating homoepitaxial films from the substrates made from the same crystalline material as the epitaxial film This new method of laser separation is based on using the selective doping of the substrate and epitaxial film with fine donor and acceptor impurities. In selective doping, concentration of free carries in the epitaxial film and substrate may essentially differ and this can lead to strong difference between the light absorption factors in the infrared region near the residual beams region where free carriers and phonon-plasmon interaction of the optical phonons with free carriers make an essential contribution to infrared absorption of the optical phonons. With the appropriate selection of the doping levels and frequency of infrared laser radiation it is possible to achieve that laser radiation is absorbed in general in the region of strong doping near the interface substrate-homoepitaxial film When scanning the interface substrate-homoepitaxial film with the focused laser beam of sufficient power, thermal decomposition of the semiconductor crystal takes place with subsequent separation of the homoepitaxial film The advantage of the proposed variations of the method for laser separation of epitaxial films in comparison with the known ones is in that it allows to separate homoepitaxial films from the substrates, i.e., homoepitaxial films having the same width of the forbidden gap as the initial semi-conductor substrate has. The proposed variations of the method can be used for separation of the epitaxial films. Besides, the proposed method allows using the high-effective and inexpensive infrared gas silicon dioxide CO2 or silicon oxide CO lasers for separation of the epitaxial films.

Abstract translation: 本发明提出了激光分离方法的变化，其允许从与外延膜相同的结晶材料制成的基板上分离同质外延膜。这种新的激光分离方法是基于使用精细施主对衬底和外延膜的选择性掺杂， 受体杂质。 在选择性掺杂中，外延膜和衬底中的自由载流子的浓度可能基本上不同，并且这可能导致残余光束区域附近的红外区域中的光吸收因子之间的强烈差异，其中自由载流子和光子声子的声子等离子体相互作用 自由载体对光学声子的红外吸收作出重要贡献。 通过适当选择红外激光辐射的掺杂水平和频率，可以实现激光辐射通常在接近衬底 - 同质外延膜附近的强掺杂区域被吸收。当用界面衬底 - 同轴外延膜与聚焦 具有足够功率的激光束，半导体晶体的热分解随着同质外延膜的分离而发生。与已知的相比，所提出的用于激光分离外延膜的方法的改进的优点在于它允许分离同质外延 来自基板的膜，即具有与初始半导体基板相同宽度的禁带间隙的同质外延膜。 所提出的方法的变型可用于分离外延膜。 此外，所提出的方法允许使用高效且廉价的红外气体二氧化硅CO 2或氧化硅CO激光器来分离外延膜。

公开(公告)号：US20140191243A1

公开(公告)日：2014-07-10

申请号：US13736372

申请日：2013-01-08

Applicant: SINMAT, INC. ,  UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC.

Inventor： RAJIV K. SINGH ,  PURUSHOTTAM KUMAR ,  DEEPIKA SINGH

IPC: H01L33/60 ,  H01L21/02 ,  H01L33/00 ,  F21V5/00 ,  F21V7/22

CPC classification number: H01L21/02518 ,  H01L33/007 ,  H01L33/10

Abstract: A patterned article includes a substrate support having planar substrate surface portions including a substrate material having a substrate refractive index. A patterned surface is on the substrate support including a plurality of features lateral to the planar substrate surface portions protruding above a height of the planar substrate surface portions. At least a top surface of the plurality of features include an epi-blocking layer including at least one of (i) a non-single crystal material having a refractive index lower as compared to the substrate refractive index and (ii) a reflecting metal or a metal alloy (reflecting material). The epi-blocking layer is not on the planar substrate surface portions.

Abstract translation: 图案化的制品包括具有平面衬底表面部分的衬底支撑件，其包括具有衬底折射率的衬底材料。 图案化表面在衬底支撑件上，包括在平面衬底表面部分的高度之上突出的平面衬底表面部分的侧面的多个特征。 多个特征的至少顶表面包括外延阻挡层，其包括以下中的至少一个：（i）与基板折射率相比折射率较低的非单晶材料和（ii）反射金属或 金属合金（反射材料）。 外阻挡层不在平面基板表面部分上。

公开(公告)号：US20140048857A1

公开(公告)日：2014-02-20

申请号：US14054123

申请日：2013-10-15

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Balasubramanian S. HARAN ,  Shom PONOTH ,  Theodorus E. STANDAERT ,  Tenko YAMASHITA

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02518 ,  H01L21/02636 ,  H01L21/265 ,  H01L29/66477 ,  H01L29/6681 ,  H01L29/785

Abstract: A process fabricates a fin field-effect-transistor by implanting a dopant into an exposed portion of a semiconductor substrate within a cavity. The cavity is formed in a dielectric layer on the semiconductor substrate. The cavity exposes the portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate. A height of the cavity defines a height of the epitaxially grown semiconductor.

Abstract translation: 工艺通过将掺杂剂注入腔内的半导体衬底的暴露部分来制造鳍状场效应晶体管。 空腔形成在半导体衬底上的电介质层中。 空腔将半导体衬底的部分暴露在空腔内。 在半导体衬底的掺杂剂注入的暴露部分的顶部的腔内外延生长半导体层。 空腔的高度限定外延生长的半导体的高度。

公开(公告)号：US20130334670A1

公开(公告)日：2013-12-19

申请号：US13716011

申请日：2012-12-14

Applicant: SK HYNIX INC.

Inventor： Seung Beom BAEK ,  Su Jin CHAE ,  Min Yong LEE ,  Hye Jin SEO ,  Young Ho LEE ,  Jin Ku LEE ,  Jong Chul LEE

IPC: H01L29/868 ,  H01L21/02

CPC classification number: H01L29/868 ,  H01L21/02518 ,  H01L21/22 ,  H01L29/165 ,  H01L29/36 ,  H01L29/66136

Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a first type semiconductor layer doped with an N type ion, a second type semiconductor layer formed over the first type semiconductor layer, and a silicon germanium (SiGe) layer doped with a P type ion formed over the second type semiconductor layer.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括掺杂有N型离子的第一类型半导体层，在第一类型半导体层上形成的第二类型半导体层和在第二类型半导体层上形成的掺杂有P型离子的硅锗（SiGe）层 。

公开(公告)号：US20130171784A1

公开(公告)日：2013-07-04

申请号：US13777803

申请日：2013-02-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luan C. Tran

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L21/76816 ,  H01L21/02518 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28273 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0705 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11546 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/66477 ,  H01L29/66825 ,  H01L29/788

Abstract: Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other.

公开(公告)号：US20130102119A1

公开(公告)日：2013-04-25

申请号：US13614885

申请日：2012-09-13

Applicant: Kangguo CHENG ,  Balasubramanian S. HARAN ,  Shom PONOTH ,  Theodorus E. STANDAERT ,  Tenko YAMASHITA

Inventor： Kangguo CHENG ,  Balasubramanian S. HARAN ,  Shom PONOTH ,  Theodorus E. STANDAERT ,  Tenko YAMASHITA

IPC: H01L21/336

CPC classification number: H01L29/66795 ,  H01L21/02518 ,  H01L21/02636 ,  H01L21/265 ,  H01L29/66477 ,  H01L29/6681 ,  H01L29/785

Abstract: A fin field-effect-transistor fabricated by forming a dummy fin structure on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. The dielectric layer surrounds the dummy fin structure. The dummy fin structure is removed to form a cavity within the dielectric layer. The cavity exposes a portion of the semiconductor substrate thereby forming an exposed portion of the semiconductor substrate within the cavity. A dopant is implanted into the exposed portion of the semiconductor substrate within the cavity thereby creating a dopant implanted exposed portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate.

Abstract translation: 通过在半导体衬底上形成虚拟鳍结构制造的鳍状场效晶体管。 在半导体衬底上形成电介质层。 电介质层围绕虚拟翅片结构。 去除虚拟翅片结构以在电介质层内形成空腔。 空腔暴露半导体衬底的一部分，从而在腔内形成半导体衬底的暴露部分。 将掺杂剂注入到空腔内的半导体衬底的暴露部分中，从而在腔内形成掺杂剂注入的半导体衬底的暴露部分。 在半导体衬底的掺杂剂注入的暴露部分的顶部的腔内外延生长半导体层。