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1.发明授权公开(公告)号：US09190471B2
公开(公告)日：2015-11-17
申请号：US13446350
申请日：2012-04-13
CPC分类号： H01L29/66636 , H01L21/02532 , H01L21/02579 , H01L21/02609 , H01L21/84 , H01L29/0657 , H01L29/0847 , H01L29/78
摘要： A semiconductor structure including a semiconductor wafer. The semiconductor wafer includes a gate structure, a first trench in the semiconductor wafer adjacent to a first side of the gate structure and a second trench adjacent to a second side of the gate structure, the first and second trenches filled with a doped epitaxial silicon to form a source in the filled first trench and a drain in the filled second trench such that each of the source and drain are recessed and have an inverted facet. In a preferred exemplary embodiment, the epitaxial silicon is doped with boron.
摘要翻译： 包括半导体晶片的半导体结构。 所述半导体晶片包括栅极结构，所述半导体晶片中与所述栅极结构的第一侧相邻的第一沟槽和与所述栅极结构的第二侧相邻的第二沟槽，所述第一和第二沟槽填充有掺杂的外延硅， 在填充的第一沟槽中形成源极，并且在填充的第二沟槽中形成漏极，使得源极和漏极中的每一个凹入并具有倒置的面。 在优选的示例性实施例中，外延硅掺杂有硼。
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公开(公告)号：US09054211B2
公开(公告)日：2015-06-09
申请号：US13540801
申请日：2012-07-03
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/8238 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823431 , H01L21/823412 , H01L21/823807 , H01L21/823821 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/785
摘要： An FET device structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins.
摘要翻译： FET器件结构具有具有Si基材料的翅片的Fin-FET器件。 氧化物元件邻接翅片并对翅片施加压力。 Fin-FET器件通道由于鳍上的压力而受到压缩应力。 另外的FET器件结构具有Fin-FET器件。 垂直于翅片排延伸的氧化物元件邻接散热片并对翅片施加压力。 Fin-FET器件的器件通道由于鳍片上的压力而受到压缩应力。
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公开(公告)号：US09048339B2
公开(公告)日：2015-06-02
申请号：US13606448
申请日：2012-09-07
申请人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/84 , H01L29/66 , H01L27/108 , H01L27/12
CPC分类号： H01L28/60 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/1203 , H01L29/66181
摘要： A method of forming a deep trench capacitor in a semiconductor-on-insulator substrate is provided. The method may include providing a pad layer positioned above a bulk substrate, etching a deep trench into the pad layer and the bulk substrate extending from a top surface of the pad layer down to a location within the bulk substrate, and doping a portion of the bulk substrate to form a buried plate. The method further including depositing a node dielectric, an inner electrode, and a dielectric cap substantially filling the deep trench, the node dielectric being located between the buried plate and the inner electrode, the dielectric cap being located at a top of the deep trench, removing the pad layer, growing an insulator layer on top of the bulk substrate, and growing a semiconductor-on-insulator layer on top of the insulator layer.
摘要翻译： 提供了在绝缘体上半导体衬底中形成深沟槽电容器的方法。 该方法可以包括提供定位在大块衬底之上的衬垫层，将深沟槽蚀刻到衬垫层中，以及从衬垫层的顶表面延伸到体衬底内的位置的本体衬底，以及掺杂 散装衬底形成掩埋板。 该方法还包括沉积基本上填充深沟槽的节点电介质，内部电极和电介质帽，节点电介质位于掩埋板和内部电极之间，电介质帽位于深沟槽的顶部， 去除衬垫层，在本体衬底的顶部上生长绝缘体层，以及在绝缘体层的顶部上生长绝缘体上半导体层。
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公开(公告)号：US08994085B2
公开(公告)日：2015-03-31
申请号：US13551714
申请日：2012-07-18
申请人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni , Tenko Yamashita , Chun-Chen Yeh
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119 , H01L21/84 , H01L27/11 , H01L27/12
CPC分类号： H01L21/84 , H01L27/10861 , H01L27/1087 , H01L27/10873 , H01L27/10894 , H01L27/10897 , H01L27/1108 , H01L27/1116 , H01L27/1203 , H01L29/945
摘要： An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.
摘要翻译： 一种集成电路，包括N +型层，设置在N +型层上的缓冲层; 形成在缓冲层上的P型区域; 覆盖N +型层的绝缘体层，覆盖绝缘体层的硅层，形成在硅层中并与延伸到N +型层的沟槽电容器的导电节点连接的嵌入式RAM FET，N +型层形成 沟槽电容器的平板电极，通过硅层和绝缘层的第一接触并且电连接到N +型层，形成在P型区域上方的硅层中的第一逻辑RAM FET，P型区域用作 第一逻辑RAM FET的P型背栅，以及通过硅层和绝缘层的第二接触，并且电连接到P型区域。
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公开(公告)号：US08987070B2
公开(公告)日：2015-03-24
申请号：US13611182
申请日：2012-09-12
IPC分类号： H01L21/00 , H01L21/762 , H01L21/84 , H01L27/12 , H01L29/06 , H01L29/66 , H01L29/786
CPC分类号： H01L27/1203 , H01L21/31144 , H01L21/76283 , H01L21/84 , H01L29/06 , H01L29/66772 , H01L29/78654
摘要： A semiconductor substrate having an isolation region and method of forming the same. The method includes the steps of providing a substrate having a substrate layer, a buried oxide (BOX), a silicon on insulator (SOI) layer, a pad oxide layer, and a pad nitride layer, forming a shallow trench region, etching the pad oxide layer to form ears and etching the BOX layer to form undercuts, depositing a liner on the shallow trench region, depositing a soft mask over the surface of the shallow trench region, filling the shallow trench region, etching the soft mask so that it is recessed to the top of the BOX layer, etching the liner off certain regions, removing the soft mask, and filling and polishing the shallow trench region. The liner prevents shorting of the semiconductor device when the contacts are misaligned.
摘要翻译： 具有隔离区域的半导体基板及其形成方法。 该方法包括以下步骤：提供具有衬底层，掩埋氧化物（BOX），绝缘体上硅（SOI）层，衬垫氧化物层和衬垫氮化物层的衬底，形成浅沟槽区，蚀刻衬垫 氧化层以形成耳朵并蚀刻BOX层以形成底切，在浅沟槽区域上沉积衬垫，在浅沟槽区域的表面上沉积软掩模，填充浅沟槽区域，蚀刻软掩模，使得它 凹陷到BOX层的顶部，在某些区域蚀刻衬垫，去除软掩模，以及填充和抛光浅沟槽区域。 当触点不对准时，衬垫防止半导体器件的短路。
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6.发明授权Epitaxial semiconductor resistor with semiconductor structures on same substrate 有权外延半导体电阻，半导体结构在同一基板上公开(公告)号：US08956938B2
公开(公告)日：2015-02-17
申请号：US13472747
申请日：2012-05-16
IPC分类号： H01L21/336 , H01L27/088
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0629 , H01L27/13 , H01L28/20 , H01L29/0649 , H01L29/36 , H01L29/41783
摘要： An electrical device is provided that includes a substrate having an upper semiconductor layer, a buried dielectric layer and a base semiconductor layer. At least one isolation region is present in the substrate that defines a semiconductor device region and a resistor device region. The semiconductor device region includes a semiconductor device having a back gate structure that is present in the base semiconductor layer. Electrical contact to the back gate structure is provided by doped epitaxial semiconductor pillars that extend through the buried dielectric layer. An epitaxial semiconductor resistor is present in the resistor device region. Undoped epitaxial semiconductor pillars extending from the epitaxial semiconductor resistor to the base semiconductor layer provide a pathway for heat generated by the epitaxial semiconductor resistor to be dissipated to the base semiconductor layer. The undoped and doped epitaxial semiconductor pillars are composed of the same epitaxial semiconductor material.
摘要翻译： 提供了一种电气装置，其包括具有上半导体层，埋入介质层和基底半导体层的衬底。 衬底中存在至少一个限定半导体器件区域和电阻器器件区域的隔离区域。 半导体器件区域包括具有存在于基极半导体层中的背栅极结构的半导体器件。 与背栅结构的电接触由穿过掩埋介电层的掺杂的外延半导体柱提供。 外延半导体电阻存在于电阻器件区域中。 从外延半导体电阻器延伸到基底半导体层的未掺杂的外延半导体柱提供了由外延半导体电阻器产生的用于散发到基极半导体层的热通路。 未掺杂和掺杂的外延半导体柱由相同的外延半导体材料组成。
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公开(公告)号：US08889564B2
公开(公告)日：2014-11-18
申请号：US13600324
申请日：2012-08-31
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , B82Y99/00 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/3086 , H01L29/0669 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66742 , H01L29/78696 , Y10S977/938
摘要： A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single crystalline semiconductor layer by selective epitaxy. A first spacer is formed around an upper portion of the mandrel. The epitaxial semiconductor layer is vertically recessed employing the first spacers as an etch mask. A second spacer is formed on sidewalls of the first spacer and vertical portions of the epitaxial semiconductor layer. Horizontal bottom portions of the epitaxial semiconductor layer are etched from underneath the vertical portions of the epitaxial semiconductor layer to form a suspended ring-shaped semiconductor fin that is attached to the mandrel. A center portion of the mandrel is etched employing a patterned mask layer that covers two end portions of the mandrel. A suspended semiconductor fin is provided, which is suspended by a pair of support structures.
摘要翻译： 具有垂直平面的心轴形成在单晶半导体层上。 通过选择性外延在单晶半导体层上形成外延半导体层。 围绕心轴的上部形成第一间隔件。 使用第一间隔物作为蚀刻掩模，外延半导体层垂直凹入。 在第一间隔物的侧壁和外延半导体层的垂直部分上形成第二间隔物。 从外延半导体层的垂直部分的下方蚀刻外延半导体层的水平底部部分，以形成附接到心轴的悬挂的环形半导体鳍片。 使用覆盖心轴的两个端部的图案化掩模层来蚀刻心轴的中心部分。 提供悬挂的半导体鳍片，其由一对支撑结构悬挂。
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公开(公告)号：US08853750B2
公开(公告)日：2014-10-07
申请号：US13457529
申请日：2012-04-27
IPC分类号： H01L29/76
CPC分类号： H01L29/66795 , H01L21/26506 , H01L21/823412 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L29/36 , H01L29/7848 , H01L29/7851
摘要： A channel region of a finFET has fins having apexes in a first direction parallel to a surface of a substrate, each fin extending downwardly from the apex, with a gate overlying the apexes and between adjacent fins. A semiconductor stressor region extends in at least the first direction away from the fins to apply a stress to the channel region. Source and drain regions of the finFET can be separated from one another by the channel region, with the source and/or drain at least partly in the semiconductor stressor region. The stressor region includes a first semiconductor region and a second semiconductor region overlying and extending from the first semiconductor region. The second semiconductor region can be more heavily doped than the first semiconductor region, and the first and second semiconductor regions can have opposite conductivity types where at least a portion of the second semiconductor region meets the first semiconductor region.
摘要翻译： finFET的沟道区域具有鳍片，鳍片具有平行于衬底表面的第一方向的顶点，每个鳍片从顶点向下延伸，栅极覆盖顶点和相邻鳍片之间。 半导体应力区域至少沿着第一方向延伸离开翅片，以对通道区域施加应力。 鳍状物FET的源极和漏极区域可以通过沟道区域彼此分离，源极和/或漏极至少部分地在半导体应力区域中。 应力区域包括覆盖并从第一半导体区域延伸的第一半导体区域和第二半导体区域。 第二半导体区域可以比第一半导体区域更重掺杂，并且第一和第二半导体区域可以具有相反的导电类型，其中第二半导体区域的至少一部分与第一半导体区域相交。
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公开(公告)号：US08841188B2
公开(公告)日：2014-09-23
申请号：US13604658
申请日：2012-09-06
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/823821 , H01L27/0924 , H01L29/0684 , H01L29/1054 , H01L29/66795
摘要： A method of forming a semiconductor device that includes forming a material stack on a semiconductor substrate, the material stack including a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, wherein the second dielectric layer is a high-k dielectric. Openings are formed through the material stack to expose a surface of the semiconductor substrate. A semiconductor material is formed in the openings through the material stack. The first dielectric layer is removed selectively to the second dielectric layer and the semiconductor material. A gate structure is formed on a channel portion of the semiconductor material. In some embodiments, the method may provide a plurality of finFET or trigate semiconductor device in which the fin structures of those devices have substantially the same height.
摘要翻译： 一种形成半导体器件的方法，包括在半导体衬底上形成材料堆叠，所述材料堆叠包括在所述衬底上的第一介电层，所述第一电介质层上的第二电介质层和所述第二电介质层上的第三电介质层 ，其中所述第二电介质层是高k电介质。 通过材料堆叠形成开口以暴露半导体衬底的表面。 通过材料堆叠在开口中形成半导体材料。 第一电介质层被选择性地去除到第二电介质层和半导体材料。 栅极结构形成在半导体材料的沟道部分上。 在一些实施例中，该方法可以提供多个finFET或者触发半导体器件，其中这些器件的鳍结构具有基本上相同的高度。
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公开(公告)号：US08841185B2
公开(公告)日：2014-09-23
申请号：US13584176
申请日：2012-08-13
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L28/92 , H01L27/0805 , H01L29/785
摘要： A high density bulk fin capacitor is disclosed. Fin capacitors are formed near finFETs by further etching the fin capacitors to provide more surface area, resulting in increased capacitance density. Embodiments of the present invention include depletion-mode varactors and inversion-mode varactors.
摘要翻译： 公开了一种高密度散装散热片电容器。 通过进一步蚀刻散热片电容器以提供更多的表面积，从而在finFET附近形成翅片电容器，从而增加电容密度。 本发明的实施例包括耗尽型变容二极管和反模式变容二极管。
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