公开(公告)号：US20140068541A1

公开(公告)日：2014-03-06

申请号：US14069855

申请日：2013-11-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： David V. HORAK ,  Charles W. KOBURGER, III ,  Shom PONOTH ,  Chih-Chao YANG

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  H01L21/76834 ,  H01L21/76885

Abstract: A method of forming a semiconductor structure includes forming a sacrificial conductive material layer. The method also includes forming a trench in the sacrificial conductive material layer. The method further includes forming a conductive feature in the trench. The method additionally includes removing the sacrificial conductive material layer selective to the conductive feature. The method also includes forming an insulating layer around the conductive feature to embed the conductive feature in the insulating layer.

Abstract translation: 形成半导体结构的方法包括形成牺牲导电材料层。 该方法还包括在牺牲导电材料层中形成沟槽。 该方法还包括在沟槽中形成导电特征。 该方法还包括去除对导电特征有选择性的牺牲导电材料层。 该方法还包括在导电特征周围形成绝缘层以将导电特征嵌入绝缘层。

公开(公告)号：US20140045312A1

公开(公告)日：2014-02-13

申请号：US14054107

申请日：2013-10-15

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Balasubramanian S. HARAN ,  Shom PONOTH ,  Theodorus E. STANDAERT ,  Tenko YAMASHITA

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02518 ,  H01L21/02636 ,  H01L21/265 ,  H01L29/66477 ,  H01L29/6681 ,  H01L29/785

Abstract: A process fabricates a fin field-effect-transistor by forming a dummy fin structure on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. The dielectric layer surrounds the dummy fin structure. The dummy fin structure is removed to form a cavity within the dielectric layer. The cavity exposes a portion of the semiconductor substrate thereby forming an exposed portion of the semiconductor substrate within the cavity. A dopant is implanted into the exposed portion of the semiconductor substrate within the cavity thereby creating a dopant implanted exposed portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate.

Abstract translation: 一种工艺通过在半导体衬底上形成虚拟鳍结构来制造鳍状场效应晶体管。 在半导体衬底上形成电介质层。 电介质层围绕虚拟翅片结构。 去除虚拟翅片结构以在电介质层内形成空腔。 空腔暴露半导体衬底的一部分，从而在腔内形成半导体衬底的暴露部分。 将掺杂剂注入到空腔内的半导体衬底的暴露部分中，从而在腔内形成掺杂剂注入的半导体衬底的暴露部分。 在半导体衬底的掺杂剂注入的暴露部分的顶部的腔内外延生长半导体层。

公开(公告)号：US20140295647A1

公开(公告)日：2014-10-02

申请号：US14054152

申请日：2013-10-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo CHENG ,  Balasubramanian S. HARAN ,  Shom PONOTH ,  Theodorus E. STANDAERT ,  Tenko YAMASHITA

IPC: H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/02518 ,  H01L21/02636 ,  H01L21/265 ,  H01L29/66477 ,  H01L29/6681 ,  H01L29/785

Abstract: A computer program storage product includes instructions for forming a fin field-effect-transistor. The instructions are configured to perform a method. The method includes implanting a dopant into an exposed portion of a semiconductor substrate within a cavity. The cavity is formed in a dielectric layer on the semiconductor substrate. The cavity exposes the portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate. A height of the cavity defines a height of the epitaxially grown semiconductor.

Abstract translation: 计算机程序存储产品包括用于形成鳍状场效应晶体管的指令。 指令被配置为执行一种方法。 该方法包括将掺杂剂注入腔内的半导体衬底的暴露部分。 空腔形成在半导体衬底上的电介质层中。 空腔将半导体衬底的部分暴露在空腔内。 在半导体衬底的掺杂剂注入的暴露部分的顶部的腔内外延生长半导体层。 空腔的高度限定外延生长的半导体的高度。

公开(公告)号：US20140264496A1

公开(公告)日：2014-09-18

申请号：US14031111

申请日：2013-09-19

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Balasubramanian S. HARAN ,  Shom PONOTH ,  Theodorus E. STANDAERT ,  Tenko YAMASHITA

IPC: H01L29/78

CPC classification number: H01L27/1211 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/785

Abstract: A non-planar semiconductor with enhanced strain includes a substrate and at least one semiconducting fin formed on a surface of the substrate. A gate stack is formed on a portion of the at least one semiconducting fin. A stress liner is formed over at least each of a plurality of sidewalls of the at least one semiconducting fin and the gate stack. The stress liner imparts stress to at least a source region, a drain region, and a channel region of the at least one semiconducting fin. The channel region is located in at least one semiconducting fin beneath the gate stack.

Abstract translation: 具有增强应变的非平面半导体包括衬底和形成在衬底的表面上的至少一个半导体鳍。 栅极堆叠形成在至少一个半导体鳍片的一部分上。 在至少一个半导体翅片和栅极叠层的多个侧壁中的至少每一个上形成应力衬垫。 应力衬垫向至少一个半导体鳍片的源极区域，漏极区域和沟道区域施加应力。 沟道区域位于栅堆叠下方的至少一个半导体鳍片中。

公开(公告)号：US20130210206A1

公开(公告)日：2013-08-15

申请号：US13852428

申请日：2013-03-28

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Balasubramanian S. HARAN ,  Shom PONOTH ,  Theodorus E. STANDAERT ,  Tenko YAMASHITA

IPC: H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/02518 ,  H01L21/02636 ,  H01L21/265 ,  H01L29/66477 ,  H01L29/6681 ,  H01L29/785

Abstract: A fin field-effect-transistor fabricated by forming a dummy fin structure on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. The dielectric layer surrounds the dummy fin structure. The dummy fin structure is removed to form a cavity within the dielectric layer. The cavity exposes a portion of the semiconductor substrate thereby forming an exposed portion of the semiconductor substrate within the cavity. A dopant is implanted into the exposed portion of the semiconductor substrate within the cavity thereby creating a dopant implanted exposed portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate.

公开(公告)号：US20140110794A1

公开(公告)日：2014-04-24

申请号：US13654717

申请日：2012-10-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Ruilong XIE ,  Xiuyu CAI ,  Pranatharthiharan BALASUBRAMANIAN ,  Shom PONOTH

IPC: H01L21/283 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76837 ,  H01L21/76897 ,  H01L29/6653

Abstract: Methods of facilitating replacement gate processing and semiconductor devices formed from the methods are provided. The methods include, for instance, providing a plurality of sacrificial gate electrodes with sidewall spacers, the sacrificial gate electrodes with sidewall spacers being separated by, at least in part, a first dielectric material, wherein the first dielectric material is recessed below upper surfaces of the sacrificial gate electrodes, and the upper surfaces of the sacrificial gate electrodes are exposed and coplanar; conformally depositing a protective film over the sacrificial gate electrodes, the sidewall spacers, and the first dielectric material; providing a second dielectric material over the protective film, and planarizing the second dielectric material, stopping on and exposing the protective film over the sacrificial gate electrodes; and opening the protective film over the sacrificial gate electrodes to facilitate performing a replacement gate process.

Abstract translation: 提供了便于更换栅极处理的方法和由该方法形成的半导体器件。 所述方法包括例如提供具有侧壁间隔物的多个牺牲栅电极，具有侧壁间隔物的牺牲栅电极至少部分地由第一介电材料隔开，其中第一介电材料凹入下 牺牲栅电极和牺牲栅电极的上表面暴露并共面; 在牺牲栅电极，侧壁间隔物和第一介电材料上保形地沉积保护膜; 在所述保护膜上提供第二电介质材料，并且平坦化所述第二电介质材料，停止所述保护膜并在所述牺牲栅电极上暴露所述保护膜; 并且在牺牲栅电极之上打开保护膜以便于执行替换浇口工艺。

公开(公告)号：US20140048857A1

公开(公告)日：2014-02-20

申请号：US14054123

申请日：2013-10-15

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Balasubramanian S. HARAN ,  Shom PONOTH ,  Theodorus E. STANDAERT ,  Tenko YAMASHITA

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02518 ,  H01L21/02636 ,  H01L21/265 ,  H01L29/66477 ,  H01L29/6681 ,  H01L29/785

Abstract: A process fabricates a fin field-effect-transistor by implanting a dopant into an exposed portion of a semiconductor substrate within a cavity. The cavity is formed in a dielectric layer on the semiconductor substrate. The cavity exposes the portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate. A height of the cavity defines a height of the epitaxially grown semiconductor.

Abstract translation: 工艺通过将掺杂剂注入腔内的半导体衬底的暴露部分来制造鳍状场效应晶体管。 空腔形成在半导体衬底上的电介质层中。 空腔将半导体衬底的部分暴露在空腔内。 在半导体衬底的掺杂剂注入的暴露部分的顶部的腔内外延生长半导体层。 空腔的高度限定外延生长的半导体的高度。

公开(公告)号：US20140326698A1

公开(公告)日：2014-11-06

申请号：US14276360

申请日：2014-05-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ya OU ,  Shom PONOTH ,  Terry A. SPOONER

IPC: C23F4/00

CPC classification number: C23F4/00 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76849 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure and method of fabricating the same is provided. More specifically, the interconnect structure is a defect free capped interconnect structure. The structure includes a conductive material formed in a trench of a planarized dielectric layer which is devoid of cap material. The structure further includes the cap material formed on the conductive material to prevent migration. The method of forming a structure includes selectively depositing a sacrificial material over a dielectric material and providing a metal capping layer over a conductive layer within a trench of the dielectric material. The method further includes removing the sacrificial material with any unwanted deposited or nucleated metal capping layer thereon.

公开(公告)号：US20140264598A1

公开(公告)日：2014-09-18

申请号：US13840069

申请日：2013-03-15

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Balasubramanian S. HARAN ,  Shom PONOTH ,  Theodorus E. STANDAERT ,  Tenko YAMASHITA

IPC: H01L27/12 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/785

Abstract: A non-planar semiconductor with enhanced strain includes a substrate and at least one semiconducting fin formed on a surface of the substrate. A gate stack is formed on a portion of the at least one semiconducting fin. A stress liner is formed over at least each of a plurality of sidewalls of the at least one semiconducting fin and the gate stack. The stress liner imparts stress to at least a source region, a drain region, and a channel region of the at least one semiconducting fin. The channel region is located in at least one semiconducting fin beneath the gate stack.

公开(公告)号：US20140217592A1

公开(公告)日：2014-08-07

申请号：US14251728

申请日：2014-04-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ya OU ,  Shom PONOTH ,  Terry A. SPOONER

IPC: H01L23/522 ,  H01L23/532

CPC classification number: C23F4/00 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76849 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure and method of fabricating the same is provided. More specifically, the interconnect structure is a defect free capped interconnect structure. The structure includes a conductive material formed in a trench of a planarized dielectric layer which is devoid of cap material. The structure further includes the cap material formed on the conductive material to prevent migration. The method of forming a structure includes selectively depositing a sacrificial material over a dielectric material and providing a metal capping layer over a conductive layer within a trench of the dielectric material. The method further includes removing the sacrificial material with any unwanted deposited or nucleated metal capping layer thereon.

Abstract translation: 提供了互连结构及其制造方法。 更具体地，互连结构是无缺陷的封装互连结构。 该结构包括形成在没有帽材料的平坦化介电层的沟槽中的导电材料。 该结构还包括形成在导电材料上以防止迁移的盖材料。 形成结构的方法包括在电介质材料上选择性地沉积牺牲材料，并在介电材料的沟槽内的导电层上提供金属覆盖层。 该方法还包括用其上的任何不需要的沉积或有核的金属覆盖层去除牺牲材料。