公开(公告)号：US09710323B2

公开(公告)日：2017-07-18

申请号：US13997850

申请日：2012-03-31

Applicant: Kuljit Singh Bains ,  George Vergis

Inventor： Kuljit Singh Bains ,  George Vergis

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/42 ,  G11C5/04 ,  G11C7/10 ,  G11C29/44 ,  G11C29/04

CPC classification number: G06F11/10 ,  G06F11/108 ,  G11C5/04 ,  G11C7/1063 ,  G11C29/42 ,  G11C29/44 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A memory subsystem has multiple memory devices coupled to a command/address line and an error alert line, the error alert line delay-compensated to provide deterministic alert signal timing. The command/address line and the error alert line are connected between the memory devices and a memory controller that manages the memory devices. The command/address line is driven by the memory controller, and the error alert line is driven by the memory devices.

公开(公告)号：US20170179980A1

公开(公告)日：2017-06-22

申请号：US15173446

申请日：2016-06-03

Applicant: SK Hynix Inc.

Inventor： Yi-Min Lin ,  Aman Bhatia ,  Naveen Kumar ,  Johnson Yen

IPC: H03M13/29 ,  G06F11/10 ,  G11C29/52 ,  H03M13/45

CPC classification number: H03M13/2963 ,  G06F11/1012 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/3602 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2909 ,  H03M13/2918 ,  H03M13/2948 ,  H03M13/2957 ,  H03M13/2975 ,  H03M13/3738 ,  H03M13/451 ,  H03M13/6561

Abstract: Techniques are described for decoding a message. In one example, the techniques include obtaining a first message comprising a plurality of information bits and a plurality of parity bits, decoding the first message using an iterative decoding algorithm to generate a first bit sequence, generating a miscorrection metric based at least on the first bit sequence and one or more reliability values corresponding to one or more bits in the first message, determining whether a miscorrection happened in the decoder by comparing the miscorrection metric with a first threshold, and upon determining that a miscorrection did not happen, outputting the first bit sequence as a decoded message.

公开(公告)号：US09679661B1

公开(公告)日：2017-06-13

申请号：US15195492

申请日：2016-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zelei Guo ,  Joanna Lai ,  Deepak Raghu

IPC: G11C16/06 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G06F11/07 ,  G11C7/06 ,  G11C16/28

CPC classification number: G11C16/26 ,  G06F11/22 ,  G11C7/062 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/28 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C29/16 ,  G11C29/50004 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/1204 ,  G11C2029/5002

Abstract: Performance improvement features can improve the performance of read processes under the right conditions. In order to selectively use the performance improvement features, the system conducts active read sampling to obtain information about bit error rate and then enables the performance improvement feature(s) for future read processes based on the information about bit error rate.

公开(公告)号：US20170160934A1

公开(公告)日：2017-06-08

申请号：US15352121

申请日：2016-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HO PARK ,  CHANIK PARK

IPC: G06F3/06 ,  G11C29/52 ,  G11C16/26 ,  G06F11/10 ,  G11C16/34 ,  G11C16/10

CPC classification number: G06F3/061 ,  G06F3/0614 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3431 ,  G11C16/3495 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A method of operating a nonvolatile memory system including a memory device having a plurality of memory blocks includes selecting a source block among the plurality of memory blocks in the nonvolatile memory system, and performing a reclaim operation for the source block based on the number of program and erase cycles which have been performed on the source block.

公开(公告)号：US09659652B2

公开(公告)日：2017-05-23

申请号：US15215672

申请日：2016-07-21

Applicant: Kabushiki Kaisha Toshiba

Inventor： Yoshikazu Takeyama ,  Masaru Koyanagi ,  Akio Sugahara

IPC: G11C7/00 ,  G11C14/00 ,  G11C7/10 ,  G11C8/12 ,  G11C29/02 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/00 ,  G11C29/04

CPC classification number: G06F13/1668 ,  G06F13/36 ,  G06F13/4068 ,  G11C7/1084 ,  G11C8/12 ,  G11C14/0018 ,  G11C16/00 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/022 ,  G11C29/028 ,  G11C2029/0407 ,  G11C2029/0409

Abstract: According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal.

公开(公告)号：US20170139772A1

公开(公告)日：2017-05-18

申请号：US15256591

申请日：2016-09-04

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Zhihong Cheng ,  Yin Guo

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G11C5/005 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: Electromagnetic compatibility (EMC) of a system-on-a-chip (SoC) is enhanced by encoding at least a subset of control signals before the control signals are transmitted over a bus (e.g., a bus internal to a SoC) from a controller to an embedded nonvolatile memory (NVM). The error-detection code used causes an EMC event to introduce errors into the transmitted codewords with relatively high probability. In response to an error being detected in the transmitted codeword, a set of safeguarding operations are performed to prevent the data stored in the NVM from being uncontrollably changed.

公开(公告)号：US20170139771A1

公开(公告)日：2017-05-18

申请号：US15238216

申请日：2016-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HOI-JU CHUNG ,  SANG-UHN CHA ,  HO-YOUNG SONG ,  HYUN-JOONG KIM

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G11C29/52 ,  G11C29/70 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

公开(公告)号：US09652011B2

公开(公告)日：2017-05-16

申请号：US14513356

申请日：2014-10-14

Applicant: Infineon Technologies AG

Inventor： Mihai-Alexandru Ionescu ,  Christoph Schroers ,  Davide Cassata ,  Hubert Fischer ,  Wolfgang Horn ,  Razvan-Catalin Mialtu ,  Radu Mihaescu

IPC: G06F11/00 ,  G06F1/30 ,  G01D3/02 ,  G01D9/00 ,  G01D9/06 ,  G01D18/00 ,  G11C29/52 ,  G11C29/04 ,  G11C29/44

CPC classification number: G06F3/0619 ,  G01D3/022 ,  G01D9/005 ,  G01D9/06 ,  G01D18/008 ,  G06F1/30 ,  G06F3/064 ,  G06F3/0673 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/4402

Abstract: Embodiments relate to multi-contact sensor devices and operating methods thereof that can reduce or eliminate offset error. In embodiments, sensor devices can comprise three or more contacts, and multiple such sensor devices can be combined. The sensor devices can comprise Hall sensor devices, such as vertical Hall devices, or other sensor types in embodiments. Operating modes can be implemented for the multi-contact sensor devices which offer significant modifications of and improvements over conventional spinning current principles, including reduced residual offset.

公开(公告)号：US20170132072A1

公开(公告)日：2017-05-11

申请号：US15062557

申请日：2016-03-07

Applicant: SK hynix Inc.

Inventor： Min Su PARK

IPC: G06F11/10 ,  G11C11/408 ,  H03M13/00 ,  G11C11/406

CPC classification number: G06F11/1044 ,  G11C11/406 ,  G11C11/4082 ,  G11C11/4085 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/20 ,  G11C29/44 ,  G11C29/50016 ,  G11C29/52 ,  G11C29/76 ,  G11C29/783 ,  G11C29/789 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2211/4062 ,  H03M13/6566

Abstract: Provided is a semiconductor device including an error correction code circuit. The semiconductor device includes a bank including a memory area for storing data and an error correction for storing parity data, an error correction code calculation circuit that corrects an error of a failed cell in correspondence to the data and the parity data and outputs a flag signal activated at a time of a generation of failed data and an address activated in the bank, an address latch circuit that stores the address applied from the error correction code to calculation circuit and outputs a failed address according to the flag signal, and a fail prevention circuit that performs an operation for repairing the failed data in correspondence to the flag signal and the failed address.

公开(公告)号：US20170125126A1

公开(公告)日：2017-05-04

申请号：US15335783

申请日：2016-10-27

Applicant: FUJITSU LIMITED

Inventor： HIROYUKI NISHIMURA ,  YUKIO SUDA ,  Satoshi Nemoto

IPC: G11C29/12 ,  G11C7/22 ,  G11C7/10

CPC classification number: G11C29/12 ,  G06F13/16 ,  G11C7/10 ,  G11C7/222 ,  G11C29/022 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/36 ,  G11C29/50012 ,  G11C2029/0409

Abstract: A diagnosis method executed by a processor includes receiving signal data at a timing of a first clock signal; setting a diagnosis period to perform a diagnosis of a memory with a predetermined period; executing a write operation and a read operation of the signal data on the memory at a timing of a second clock signal that is higher in rate than the first clock signal within the diagnosis period; executing at least one of operations included in the diagnosis of the memory using diagnosis data at a timing of the second clock signal during a period responsive to a difference between a number of first clock pulses of the first clock signal within the diagnosis period and a number of second clock pulses of the second clock signal within the diagnosis period; and diagnosing the memory by repeating the diagnosis period by a plurality of times.