公开(公告)号：US20140327464A1

公开(公告)日：2014-11-06

申请号：US14331791

申请日：2014-07-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Cheng WU ,  Hsien-Pin HU ,  Shang-Yun HOU ,  Shin-Puu JENG ,  Chen-Hua YU ,  Chao-Hsiang YANG

IPC分类号： G01R31/28

CPC分类号： G01R31/2896 ,  G01R1/0416 ,  G01R31/2601 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02377 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/0614 ,  H01L2224/0616 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16238 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014

摘要： A test structure including an array of microbumps electrically connecting a chip and a substrate, wherein a width of each microbump of the array of microbumps is equal to or less than about 50 microns (μm). The test structure further includes an interconnect structure connected to the array of microbumps. The test structure further includes an array of test pads around a periphery of the array of microbumps, wherein a test pad of the array of test pads is connected to a corresponding microbump of the array of microbumps through the interconnect structure. A width of the test pad is greater than a width of the corresponding microbump, and the test pad is adapted to be covered after circuit probing by a passivation material to prevent particle and corrosion issues.

摘要翻译： 一种测试结构，其包括将芯片和基板电连接的微型阵列阵列，其中微胶片阵列的每个微型块的宽度等于或小于约50微米（μm）。 测试结构还包括连接到微丸阵列的互连结构。 该测试结构进一步包括围绕微胶片阵列周边的测试焊盘的阵列，其中测试焊盘阵列的测试焊盘通过互连结构连接到微胶片阵列的对应微型块。 测试垫的宽度大于对应的微型块的宽度，并且测试垫适于在通过钝化材料的电路探测之后被覆盖以防止颗粒和腐蚀问题。

公开(公告)号：US20240347439A1

公开(公告)日：2024-10-17

申请号：US18753091

申请日：2024-06-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shin-Puu JENG ,  Po-Hao TSAI ,  Po-Yao CHUANG ,  Feng-Cheng HSU ,  Shuo-Mao CHEN ,  Techi WONG

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L21/52 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/053 ,  H01L23/31 ,  H01L25/00 ,  H01L25/10

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/053 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L21/561 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/15311

摘要： A chip package is provided. The chip package includes a substrate structure including: a redistribution structure having a conductive pad; and an insulating layer under the redistribution structure. The chip package includes a first chip over the redistribution structure. The chip package includes a second chip under the substrate structure. A top portion of the second chip extends into the insulating layer from a bottom surface of the insulating layer, the bottom surface faces away from the first chip, and a portion of the insulating layer is between the second chip and the redistribution structure. The chip package includes a first molding layer over the redistribution structure and the first chip. A first sidewall of the first molding layer and a second sidewall of the redistribution structure are substantially level with each other.

公开(公告)号：US20240347410A1

公开(公告)日：2024-10-17

申请号：US18751724

申请日：2024-06-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Shen YEH ,  Che-Chia YANG ,  Yu-Sheng LIN ,  Chin-Hua WANG ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/04 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L23/3675 ,  H01L21/4882 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L21/56 ,  H01L23/04 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253

摘要： A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a first chip structure over the wiring substrate. The chip package structure includes a heat-spreading lid over the wiring substrate and covering the first chip structure. The heat-spreading lid includes a ring structure and a top plate, the ring structure surrounds the first chip structure, the top plate covers the ring structure and the first chip structure, and the first chip structure has a first sidewall and a second sidewall opposite to the first sidewall.

公开(公告)号：US20230378039A1

公开(公告)日：2023-11-23

申请号：US17664538

申请日：2022-05-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei CHEN ,  Meng-Liang LIN ,  Li-Ling LIAO ,  Shin-Puu JENG

IPC分类号： H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/64 ,  H01L21/48

CPC分类号： H01L23/49822 ,  H01L25/0655 ,  H01L24/16 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49838 ,  H01L23/642 ,  H01L21/4853 ,  H01L21/4857 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19103

摘要： Some implementations herein describe a semiconductor package. The semiconductor package, which may correspond to a high-performance computing semiconductor package, includes an interposer. The interposer includes tapered interconnect structures formed using a laser plug process. The tapered interconnect structures may include a length that is lesser relative to a length of the column-shaped interconnect structures formed using a through-silicon via process. Such a length reduces a thickness of the interposer and reduces a length of electrical connections through the interposer. In this way, a signal integrity may be increased and parasitics of the semiconductor package including the tapered interconnect structures may be reduced to increase a performance of the semiconductor package. Additionally, the reduced thickness of the interposer may reduce an overall thickness of the semiconductor package to save space consumed by the semiconductor package in a computing system.

公开(公告)号：US20230369150A1

公开(公告)日：2023-11-16

申请号：US18359923

申请日：2023-07-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Puu JENG ,  Feng-Cheng HSU ,  Shuo-Mao CHEN

IPC分类号： H01L23/13 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L23/13 ,  H01L23/49833 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/17 ,  H01L25/50 ,  H01L25/18

摘要： A package structure and a method of forming the same are provided. The package structure includes a package substrate, an interposer substrate, and a semiconductor device. The interposer substrate is disposed over the package substrate, wherein the interposer substrate has a bottom surface facing the package substrate and a first cavity formed on the bottom surface. The semiconductor device is disposed in the first cavity. The package substrate has a top surface facing the interposer substrate and a second cavity formed on the top surface, wherein the second cavity is configured to accommodate the semiconductor device.

公开(公告)号：US20230343724A1

公开(公告)日：2023-10-26

申请号：US18336258

申请日：2023-06-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chen LAI ,  Chin-Hua WANG ,  Ming-Chih YEW ,  Che-Chia YANG ,  Shu-Shen YEH ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

CPC分类号： H01L23/562 ,  H01L23/3135 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0655 ,  H01L21/6835 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L2924/18161 ,  H01L2224/16227 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2221/68372 ,  H01L2924/3512

摘要： A package structure is provided. The package structure includes a semiconductor die over a redistribution structure, bonding elements below the redistribution structure, and an underfill layer surrounding the bonding elements and the redistribution structure. The semiconductor die has a rectangular profile in a plan view. A pitch of the bonding elements is defined as the sum of a diameter of the bonding elements and a spacing between neighboring two of the bonding elements. A first circular area of the redistribution structure is entirely covered and in direct contact with the underfill layer. The center of the first circular area is aligned with a first corner of the rectangular profile of the semiconductor die. A diameter of the first circular area is greater than twice the pitch of the bonding elements.

公开(公告)号：US20230299017A1

公开(公告)日：2023-09-21

申请号：US18325205

申请日：2023-05-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Shen YEH ,  Che-Chia YANG ,  Chia-Kuei HSU ,  Ming-Chih YEW ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L23/053 ,  H01L23/13

CPC分类号： H01L23/562 ,  H01L21/4878 ,  H01L23/053 ,  H01L23/13

摘要： A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a substrate, an electronic component, a ring structure, and an adhesive layer. The electronic component is located over a surface of the substrate. The ring structure is located over the surface of the substrate and surrounding the electronic component. The ring structure has a bottom surface facing the surface of the substrate and a top surface opposite the bottom surface. The ring structure includes recesses recessed from and located on the top surface, wherein the recesses are arranged corresponding to the corners of the substrate. The adhesive layer is interposed between the bottom surface of the ring structure and the surface of the substrate.

公开(公告)号：US20230290702A1

公开(公告)日：2023-09-14

申请号：US18318844

申请日：2023-05-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Shen YEH ,  Che-Chia YANG ,  Chia-Kuei HSU ,  Ming-Chih YEW ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/373 ,  H01L23/58 ,  H01L23/29

CPC分类号： H01L23/373 ,  H01L23/585 ,  H01L23/29

摘要： A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, semiconductor dies over the package substrate, and an underfill element over the package substrate and surrounding the semiconductor dies. A portion of the underfill element is located between the semiconductor dies. The semiconductor die package also includes lid structures respectively attached to the top surfaces of the semiconductor dies. In plan view, each lid structure is located within the periphery of the top surface of the corresponding semiconductor die. Each lid structure is disconnected from other lid structures, and a gap is formed between adjacent lid structures and located over the portion of the underfill element.

公开(公告)号：US20230100127A1

公开(公告)日：2023-03-30

申请号：US18061501

申请日：2022-12-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Sheng LIN ,  Po-Yao LIN ,  Shu-Shen YEH ,  Chin-Hua WANG ,  Shin-Puu JENG

IPC分类号： H01L23/367 ,  H01L23/373 ,  H01L23/31 ,  H01L21/48

摘要： A semiconductor die package is provided. The semiconductor die package includes a package substrate, and a first semiconductor die and a second semiconductor die disposed thereon. A ring structure is attached to the package substrate and surrounds the semiconductor dies. A lid structure is attached to the ring structure and disposed over the semiconductor dies, and has an opening exposing the second semiconductor die. A heat sink is disposed over the lid structure and has a portion extending into the opening of the lid structure. A first thermal interface material (TIM) layer is interposed between the lid structure and the first semiconductor die. A second TIM layer is interposed between the extending portion of the heat sink and the second semiconductor die. The first TIM layer has a thermal conductivity higher than the thermal conductivity of the second TIM layer.

公开(公告)号：US20230066598A1

公开(公告)日：2023-03-02

申请号：US17460836

申请日：2021-08-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chen LAI ,  Ming-Chih YEW ,  Li-Ling LIAO ,  Chin-Hua WANG ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56

摘要： A package structure is provided. The package structure includes a redistribution structure over a substrate, a semiconductor die over the redistribution structure and electrically coupled to the substrate, and an underfill material over the substrate and encapsulating the redistribution structure and the semiconductor die. The underfill material includes an extension portion overlapping a corner of the semiconductor die and extending into the substrate.