公开(公告)号：US20180211955A1

公开(公告)日：2018-07-26

申请号：US15415446

申请日：2017-01-25

Applicant: International Business Machines Corporation

Inventor： Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Sivananda K. Kanakasabapathy ,  John R. Sporre

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/78 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

Abstract: The present invention provides fin cut techniques in a replacement gate process for finFET fabrication. In one aspect, a method of forming a finFET employs a dummy gate material to pin a lattice constant of patterned fins prior to a fin cut thereby preventing strain relaxation. A dielectric fill in a region of the fin cut (below the dummy gates) reduces an aspect ratio of dummy gates formed from the dummy gate material in the fin cut region, thereby preventing collapse of the dummy gates. FinFETs formed using the present process are also provided.

公开(公告)号：US20180190544A1

公开(公告)日：2018-07-05

申请号：US15795975

申请日：2017-10-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Peng Xu ,  Wenyu Xu

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated chips include a first device and a second device. The first device includes a stack of vertically arranged sheets of a first channel material, a source and drain region having a first dopant type, and a first work function metal layer formed from a first work function metal. The second device includes a stack of vertically arranged sheets of a second channel material, a source and drain region having a second dopant type, and a second work function metal layer formed from a second work function metal.

公开(公告)号：US10014226B2

公开(公告)日：2018-07-03

申请号：US15465891

申请日：2017-03-22

Applicant: HITACHI KOKUSAI ELECTRIC INC.

Inventor： Arito Ogawa

IPC: H01L21/28 ,  H01L21/8238 ,  H01L21/3215 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/3205

CPC classification number: H01L21/823842 ,  H01J37/321 ,  H01J37/32155 ,  H01J37/32174 ,  H01J37/32651 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/32051 ,  H01L21/3215 ,  H01L21/82345 ,  H01L27/0922 ,  H01L29/4966

Abstract: A process of forming a first mask on a first region of a metal film formed on a surface of a substrate, a process of modulating a work function of a first exposed region of the metal film, using plasma of a first process gas, a process of removing the first mask, a process of forming a second mask on a second region of the metal film, and a process of modulating the work function of a second exposed region of the metal film, using plasma of a second process gas are executed.

公开(公告)号：US20180174650A1

公开(公告)日：2018-06-21

申请号：US15884362

申请日：2018-01-30

Applicant: Attopsemi Technology Co., LTD

Inventor： Shine C. Chung

IPC: G11C13/00 ,  H01L27/12 ,  G11C11/16 ,  H01L27/092 ,  H01L45/00 ,  H01L27/24 ,  H01L27/22 ,  G11C17/16

CPC classification number: G11C13/0004 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C17/16 ,  G11C2013/0073 ,  G11C2213/72 ,  G11C2213/74 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0738 ,  H01L27/0788 ,  H01L27/0924 ,  H01L27/1211 ,  H01L27/224 ,  H01L27/228 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

Abstract: An One-Time Programmable (OTP) memory is built in at least one of semiconductor fin structures. The OTP memory has a plurality of OTP cells. At least one of the OTP cells can have at least one resistive element and at least one fin. The at least one resistive element can be built by an extended source/drain or a MOS gate. The at least one fin can be built on a common well or on an isolated structure that has at least one MOS gate dividing fins into at least one first active region and a second active region.

公开(公告)号：US10002791B1

公开(公告)日：2018-06-19

申请号：US15481012

申请日：2017-04-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Paul C. Jamison ,  ChoongHyun Lee

IPC: H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/82345 ,  H01L21/823487 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823885 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785

Abstract: A method is presented for forming a device having multiple field effect transistors (FETs) with each FET having a different work function. In particular, the method includes forming multiple microchips in which each FET has a different threshold voltage (Vt) or work-function. In one embodiment, four FETs are formed over a semiconductor substrate. Each FET has a source, drain and a gate electrode. Each gate electrode is processed independently to provide a substantially different threshold voltage.

公开(公告)号：US20180158821A1

公开(公告)日：2018-06-07

申请号：US15370555

申请日：2016-12-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Changyong XIAO ,  Xusheng WU ,  Min-hwa CHI ,  Jie CHEN

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate structures with low resistance and methods of manufacture. The structure includes: an nFET device formed in a first cavity having a first volume which is filled with conductive material; and a pFET device forming in a second cavity having a second volume greater than the first volume. The second volume being filled with the conductive material.

公开(公告)号：US09991356B2

公开(公告)日：2018-06-05

申请号：US15246262

申请日：2016-08-24

Applicant: Weize Chen ,  Richard J. de Souza ,  Md M. Hoque ,  Patrice M. Parris

Inventor： Weize Chen ,  Richard J. de Souza ,  Md M. Hoque ,  Patrice M. Parris

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8234

CPC classification number: H01L29/4933 ,  H01L21/28052 ,  H01L21/28105 ,  H01L21/823443 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/4983 ,  H01L29/66477 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

Abstract: Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel. The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.

公开(公告)号：US20180151376A1

公开(公告)日：2018-05-31

申请号：US15797340

申请日：2017-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojung Choi ,  Moonkyun Song ,  Yoon Tae Hwang ,  Kyumin Lee ,  Sangjin Hyun

IPC: H01L21/28 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/324 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L21/3105

CPC classification number: H01L21/28185 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/82345 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/78

Abstract: A method of fabricating a semiconductor device includes forming first and second gate dielectric layers on first and second regions of a semiconductor substrate, respectively, forming a first metal-containing layer on the first and second gate dielectric layers, performing a first annealing process with respect to the first metal-containing layer, removing the first metal-containing layer from the first region, forming a second metal-containing layer on an entire surface of the semiconductor substrate, performing a second annealing process with respect to the second metal-containing layer, forming a gate electrode layer on the second metal-containing layer, and partially removing the gate electrode layer, the second metal-containing layer, the first metal-containing layer, the first gate dielectric layer, and the second gate dielectric layer to form first and second gate patterns on the first and second regions, respectively.

公开(公告)号：US09960162B2

公开(公告)日：2018-05-01

申请号：US15184405

申请日：2016-06-16

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Manoj Mehrotra ,  Mahalingam Nandakumar

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/02148 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.

公开(公告)号：US20180114728A1

公开(公告)日：2018-04-26

申请号：US15836399

申请日：2017-12-08

Applicant: Zing Semiconductor Corporation

Inventor： DEYUAN XIAO

IPC: H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L21/823807 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/267 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: A complementary metal-oxide-semiconductor field-effect transistor comprises a semiconductor substrate, N-type and P-type field-effect transistors positioned in the semiconductor substrate. Each of the field-effect transistors includes a germanium nanowire, a III-V compound layer surrounding the germanium nanowire, a potential barrier layer mounted on the III-V compound layer, a gate dielectric layer, a gate, a source region and a drain region mounted on two sides of the gate. The field-effect transistor can produce two-dimensional electron gases and two-dimensional electron hole gases, and enhance the carrier mobility of the complementary metal-oxide-semiconductor field-effect transistor.