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    READ MEASUREMENT OF A PLURALITY OF RESISTIVE MEMORY CELLS
    63.
    发明申请
    READ MEASUREMENT OF A PLURALITY OF RESISTIVE MEMORY CELLS 有权
    阅读测量电阻记忆细胞的多样性

    公开(公告)号：US20140211541A1

    公开(公告)日：2014-07-31

    申请号：US14164725

    申请日：2014-01-27

    Applicant: International Business Machines Corporation

    Inventor： ABU SEBASTIAN ,  Nikolaos Papandreou ,  Charalampos Pozidis

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0061 ,  G11C2013/0057

    Abstract: A method for read measurement of a plurality N of resistive memory cells having a plurality M of programmable levels is suggested. The method includes a step of reading back from a number of reference cells to obtain a reading back parameter, a step of determining an actual read voltage for the N memory cells based on the obtained reading back parameter for obtaining a target read current at a following read measurement, and, a step of applying the determined actual read voltage to the N memory cells at the following read measurement.

    Abstract translation: 提出了一种用于读取测量具有多个可编程电平的多个N个电阻存储器单元的方法。 该方法包括从多个参考单元读取以获得回读参数的步骤，基于获得的读回参数确定N个存储单元的实际读取电压的步骤，用于获得下一个目标读取电流 读取测量，以及在以下读取测量时将所确定的实际读取电压施加到N个存储器单元的步骤。

    Semiconductor memory device
    64.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08743587B2

    公开(公告)日：2014-06-03

    申请号：US13197050

    申请日：2011-08-03

    Applicant: Satoru Takase

    Inventor： Satoru Takase

    IPC: G11C11/00 ,  G11C11/36

    CPC classification number: G11C13/0007 ,  G11C8/005 ,  G11C11/5685 ,  G11C13/0033 ,  G11C13/0069 ,  G11C14/00 ,  G11C16/3431 ,  G11C2211/5641

    Abstract: According to one embodiment, a semiconductor memory device includes first cells, first lines, second lines, a first cell array, and a signal driver. The first cell has in either a first state or a second state. Retention time in the second state is longer than in the first state. The first cell array has the first cells formed in a matrix the individuals. The first cells are electrically connected by the first, second lines. The signal driver drives the first cells. The signal driver causes the first cells to transition to either the first state or the second state by controlling any one of a voltage, a current, and a charge amount applied to the first cells, or a combination of these, and waveforms of the voltage, current, and charge amount and/or the length of transfer time of at least one of the voltage, current, and charge amount.

    Abstract translation: 根据一个实施例，半导体存储器件包括第一单元，第一行，第二行，第一单元阵列和信号驱动器。 第一个单元格处于第一状态或第二状态。 处于第二状态的保持时间长于第一状态。 第一个单元阵列具有在矩阵中形成的第一个单元。 第一个单元通过第一个第二行电连接。 信号驱动器驱动第一个单元。 信号驱动器通过控制施加到第一单元的电压，电流和电荷量中的任何一个或这些的组合以及电压的波形来使第一单元转变到第一状态或第二状态 ，电流，电荷量和/或电压，电流和电荷量中的至少一个的传输时间长度。

    Saving of data in cases of word-line to word-line short in memory arrays
    65.
    发明授权
    Saving of data in cases of word-line to word-line short in memory arrays 有权
    在字线的情况下将数据保存到存储器阵列中的字线短路

    公开(公告)号：US08730722B2

    公开(公告)日：2014-05-20

    申请号：US13411115

    申请日：2012-03-02

    Applicant: Pao-Ling Koh ,  Tien-Chien Kuo

    Inventor： Pao-Ling Koh ,  Tien-Chien Kuo

    IPC: G11C16/04

    CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5685 ,  G11C29/025 ,  G11C2029/1202

    Abstract: Technique of operating a non-volatile memory are presented so that in case data that would otherwise be lost in the case of a word line to word line short is preserved. Before writing a word line, the data from a previously written adjacent is word line is read back and stored in data latches associated with the corresponding bit lines, but that are not being used for the data to be written. If a short occurs, as the data for both word lines is still in the latches, it can be written to a new location. This technique can also be incorporated into cache write operations and for a binary write operation inserted into a pause of a multi-state write.

    Abstract translation: 呈现操作非易失性存储器的技术，以便保留在字线短到字线短的情况下否则会丢失的数据。 在写入字线之前，来自先前写入的相邻的数据是字线被读回并存储在与相应位线相关联的数据锁存器中，但是不被用于要被写入的数据。 如果发生短路，由于两条字线的数据仍在锁存器中，因此可以将其写入新位置。 这种技术也可以并入高速缓存写入操作和插入到多状态写入的暂停中的二进制写操作。

    NONVOLATILE MEMORY DEVICE USING RESISTANCE MATERIAL AND METHOD OF DRIVING THE NONVOLATILE MEMORY DEVICE
    66.
    发明申请
    NONVOLATILE MEMORY DEVICE USING RESISTANCE MATERIAL AND METHOD OF DRIVING THE NONVOLATILE MEMORY DEVICE 有权
    使用电阻材料的非易失性存储器件和驱动非易失性存储器件的方法

    公开(公告)号：US20140119094A1

    公开(公告)日：2014-05-01

    申请号：US13940856

    申请日：2013-07-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung-Yeon Lee ,  Yeong-Taek Lee

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/5607 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/71 ,  G11C2213/72

    Abstract: Provided is a nonvolatile memory device using a resistance material and a method of driving the nonvolatile memory device. The nonvolatile memory device comprises a resistive memory cell which stores multiple bits; a sensing node; a clamping unit coupled between the resistive memory cell and the sensing node and provides a clamping bias to the resistive memory cell; a compensation unit which provides a compensation current to the sensing node; a sense amplifier coupled to the sensing node and senses a change in a level of the sensing node; and an encoder which codes an output value of the sense amplifier in response to a first clock signal. The clamping bias varies over time. The compensation current is constant during a read period.

    Abstract translation: 提供了使用电阻材料的非易失性存储器件和驱动非易失性存储器件的方法。 非易失性存储器件包括存储多个位的电阻存储器单元; 感测节点; 耦合在所述电阻存储器单元和所述感测节点之间的钳位单元，并向所述电阻性存储单元提供钳位偏置; 补偿单元，其向感测节点提供补偿电流; 感测放大器耦合到感测节点并感测感测节点的电平的变化; 以及编码器，其响应于第一时钟信号对读出放大器的输出值进行编码。 钳位偏置随时间而变化。 补偿电流在读取期间是恒定的。

    Memory device manufacturing method with memory element having a metal-oxygen compound
    67.
    发明授权
    Memory device manufacturing method with memory element having a metal-oxygen compound 有权
    具有金属 - 氧化合物的记忆元件的存储器件制造方法

    公开(公告)号：US08697487B2

    公开(公告)日：2014-04-15

    申请号：US13897109

    申请日：2013-05-17

    Applicant: Macronix International Co., Ltd.

    Inventor： ChiaHua Ho ,  Erh-Kun Lai

    IPC: H01L45/00

    CPC classification number: H01L45/1683 ,  B82Y10/00 ,  G11C11/14 ,  G11C11/22 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

    Abstract: Memory devices based on tungsten-oxide memory regions are described, along with methods for manufacturing and methods for programming such devices. The tungsten-oxide memory region can be formed by oxidation of tungsten material using a non-critical mask, or even no mask at all in some embodiments. A memory device described herein includes a bottom electrode and a memory element on the bottom electrode. The memory element comprises at least one tungsten-oxygen compound and is programmable to at least two resistance states. A top electrode comprising a barrier material is on the memory element, the barrier material preventing movement of metal-ions from the top electrode into the memory element.

    Abstract translation: 描述了基于氧化钨存储区域的存储器件以及用于制造的方法以及用于编程这种器件的方法。 在一些实施例中，氧化钨存储区可以通过使用非关键掩模氧化钨材料或甚至根本不进行掩模来形成。 本文描述的存储器件包括底部电极和底部电极上的存储元件。 存储元件包括至少一种钨 - 氧化合物，并且可编程为至少两个电阻状态。 包含阻挡材料的顶部电极在存储元件上，阻挡材料防止金属离子从顶部电极移动到存储元件中。

    NONVOLATILE MEMORY ELEMENT AND NONVOLATILE MEMORY DEVICE
    68.
    发明申请
    NONVOLATILE MEMORY ELEMENT AND NONVOLATILE MEMORY DEVICE 有权
    非易失性存储元件和非易失性存储器件

    公开(公告)号：US20140061579A1

    公开(公告)日：2014-03-06

    申请号：US13995383

    申请日：2012-10-22

    Applicant: Zhiqiang Wei ,  Takeshi Takagi ,  Koji Katayama

    Inventor： Zhiqiang Wei ,  Takeshi Takagi ,  Koji Katayama

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/145 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/15 ,  H01L27/101 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1625

    Abstract: A variable resistance nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer including: a first oxide layer including a metal oxide having non-stoichiometric composition and including p-type carriers; a second oxide layer located between and in contact with the first oxide layer and a second electrode and including a metal oxide having non-stoichiometric composition and including n-type carriers; an oxygen reservoir region located in the first oxide layer, having no contact with the first electrode, and having an oxygen content atomic percentage higher than that of the first oxide layer; and a local region located in the second oxide layer, having contact with the oxygen reservoir region, and having an oxygen content atomic percentage lower than that of the second oxide layer.

    Abstract translation: 可变电阻非易失性存储元件包括第一电极，第二电极和可变电阻层，包括：包含具有非化学计量组成的金属氧化物并包括p型载流子的第一氧化物层; 位于第一氧化物层之间并与第一氧化物层接触的第二氧化物层和第二电极，并且包括具有非化学计量组成并包括n型载体的金属氧化物; 位于所述第一氧化物层中的与第一电极没有接触并且氧含量原子百分比高于第一氧化物层的氧储存区; 以及位于所述第二氧化物层中的与氧储存区接触并且氧含量原子百分比低于第二氧化物层的原子百分比的局部区域。

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