公开(公告)号：US20190385909A1

公开(公告)日：2019-12-19

申请号：US16556360

申请日：2019-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Chieh Wu ,  Tang-Kuei Chang ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ting-Kui Chang ,  Chia Hsuan Lee

IPC: H01L21/768 ,  H01L23/522

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

公开(公告)号：US09735231B2

公开(公告)日：2017-08-15

申请号：US14231099

申请日：2014-03-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jung-Chih Tsao ,  Chi-Cheng Hung ,  Yu-Sheng Wang ,  Wen-Hsi Lee ,  Kei-Wei Chen ,  Ying-Lang Wang

IPC: H01L29/06 ,  H01L21/28 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: A method includes method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer, removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A block layer is deposited over the metal layer using Atomic Layer Deposition (ALD). The remaining portion of the recess is filled with metallic materials, wherein the metallic materials are overlying the metal layer.

公开(公告)号：US09536762B2

公开(公告)日：2017-01-03

申请号：US14539844

申请日：2014-11-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Kei-Wei Chen

IPC: H05B1/02 ,  H01L21/67 ,  H05B3/00 ,  G01J5/00 ,  H01L27/146

CPC classification number: H01L21/67248 ,  G01J5/00 ,  G01J2005/0077 ,  G01J2005/0085 ,  H01L21/67115 ,  H01L27/14649 ,  H05B3/0047

Abstract: A thermal processing apparatus is provided in accordance with some embodiments. The thermal processing apparatus includes a heating source for transmitting incident radiation to a work piece having a circuit pattern formed on a front surface; a radiation sensor configured to receive light radiated from the front surface of the work piece; and a controller coupled to the radiation sensor, the controller being designed to control the heating source to reduce temperature variation of the work piece.

Abstract translation: 根据一些实施例提供热处理装置。 热处理装置包括用于将入射辐射传送到具有形成在前表面上的电路图案的工件的加热源; 辐射传感器，被配置为接收从所述工件的前表面辐射的光; 以及耦合到所述辐射传感器的控制器，所述控制器被设计成控制所述加热源以减小所述工件的温度变化。

公开(公告)号：US09368540B2

公开(公告)日：2016-06-14

申请号：US14525525

申请日：2014-10-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shiu-Ko JangJian ,  Min Hao Hong ,  Kei-Wei Chen ,  Chi-Cherng Jeng

IPC: H01L27/148 ,  H01L27/146 ,  H01L31/103 ,  H01L31/18 ,  H01L29/16 ,  H01L31/028

CPC classification number: H01L27/14645 ,  H01L27/14612 ,  H01L27/14616 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14689 ,  H01L29/16 ,  H01L31/028 ,  H01L31/103 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method includes performing a first epitaxy to grow a first epitaxy layer of a first conductivity type, and performing a second epitaxy to grow a second epitaxy layer of a second conductivity type opposite the first conductivity type over the first epitaxy layer. The first and the second epitaxy layers form a diode. The method further includes forming a gate dielectric over the first epitaxy layer, forming a gate electrode over the gate dielectric, and implanting a top portion of the first epitaxy layer and the second epitaxy layer to form a source/drain region adjacent to the gate dielectric.

Abstract translation: 一种方法包括执行第一外延以生长第一导电类型的第一外延层，以及执行第二外延以在第一外延层上生长与第一导电类型相反的第二导电类型的第二外延层。 第一和第二外延层形成二极管。 该方法还包括在第一外延层上形成栅极电介质，在栅极电介质上方形成栅电极，以及注入第一外延层和第二外延层的顶部部分，以形成与栅极电介质相邻的源极/漏极区域 。

公开(公告)号：US09070664B2

公开(公告)日：2015-06-30

申请号：US13969370

申请日：2013-08-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen

IPC: H01L21/8232 ,  H01L29/45 ,  C23C14/34 ,  H01L21/28 ,  H01L21/285 ,  C23C14/14 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/45 ,  C23C14/14 ,  C23C14/3414 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/823418 ,  H01L29/456 ,  H01L29/665 ,  Y10T29/41

Abstract: A device includes a substrate and a metal-oxide-semiconductor (MOS) device. The MOS device includes a gate dielectric over the substrate, a gate electrode over the gate dielectric, a source/drain region adjacent the gate dielectric, and a source/drain silicide over and contacting the source/drain region. The source/drain silicide comprises silicon, nickel, and a secondary metal. A ratio of a volume percentage of the secondary metal to a volume percentage of the silicon in the source/drain silicide is between about 0.005 and about 0.1. The secondary metal has a density between about 5,000 kg/m3 and about 15,000 kg/m3.

Abstract translation: 一种器件包括衬底和金属氧化物半导体（MOS）器件。 MOS器件包括在衬底上的栅极电介质，在栅极电介质上方的栅极电极，与栅极电介质相邻的源极/漏极区域，以及源极/漏极硅化物，并与源极/漏极区域接触。 源极/漏极硅化物包括硅，镍和二次金属。 源极/漏极硅化物中二次金属的体积百分比与硅的体积百分比的比率在约0.005和约0.1之间。 二次金属具有约5,000kg / m 3至约15,000kg / m 3的密度。

公开(公告)号：US20150041851A1

公开(公告)日：2015-02-12

申请号：US14525525

申请日：2014-10-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shiu-Ko JangJian ,  Min Hao Hong ,  Kei-Wei Chen ,  Chi-Cherng Jeng

IPC: H01L27/146 ,  H01L29/16 ,  H01L31/028

CPC classification number: H01L27/14645 ,  H01L27/14612 ,  H01L27/14616 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14689 ,  H01L29/16 ,  H01L31/028 ,  H01L31/103 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method includes performing a first epitaxy to grow a first epitaxy layer of a first conductivity type, and performing a second epitaxy to grow a second epitaxy layer of a second conductivity type opposite the first conductivity type over the first epitaxy layer. The first and the second epitaxy layers form a diode. The method further includes forming a gate dielectric over the first epitaxy layer, forming a gate electrode over the gate dielectric, and implanting a top portion of the first epitaxy layer and the second epitaxy layer to form a source/drain region adjacent to the gate dielectric.

Abstract translation: 一种方法包括执行第一外延以生长第一导电类型的第一外延层，以及执行第二外延以在第一外延层上生长与第一导电类型相反的第二导电类型的第二外延层。 第一外延层和第二外延层形成二极管。 该方法还包括在第一外延层上形成栅极电介质，在栅极电介质上方形成栅电极，以及注入第一外延层和第二外延层的顶部部分，以形成与栅极电介质相邻的源极/漏极区域 。

公开(公告)号：US20140213153A1

公开(公告)日：2014-07-31

申请号：US13836534

申请日：2013-03-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tang-Kuei Chang ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Wei-Jen Lo ,  Ying-Lang Wang

IPC: B24B9/06 ,  B24B21/04

CPC classification number: B24B9/065 ,  B24B21/004 ,  B24B21/04

Abstract: An embodiment wafer polishing tool includes an abrasive tape, a polish head holding the abrasive tape, and a rotation module. The rotation module is configured to rotate a wafer during a wafer polishing process, and the polish head is configured to apply pressure to the abrasive tape toward a first surface of the wafer during the wafer polishing process.

Abstract translation: 实施方式的晶片抛光工具包括研磨带，保持研磨带的抛光头和旋转模块。 旋转模块被配置为在晶片抛光过程期间旋转晶片，并且抛光头构造成在晶片抛光过程期间朝向晶片的第一表面施加压力至研磨带。

公开(公告)号：US12159925B2

公开(公告)日：2024-12-03

申请号：US17869275

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ji-Yin Tsai ,  Jung-Jen Chen ,  Pei-Ren Jeng ,  Chii-Horng Li ,  Kei-Wei Chen ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L21/223 ,  H01L29/161 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306

Abstract: In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.

公开(公告)号：US12021117B2

公开(公告)日：2024-06-25

申请号：US17574563

申请日：2022-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. ,  NATIONAL CHENG KUNG UNIVERSITY

Inventor： Te-Ming Kung ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Wen-Hsi Lee ,  Shu Wei Chang

IPC: H01L21/324 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/0673 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/324 ,  H01L21/823412 ,  H01L29/42392

Abstract: A method of forming a semiconductor structure includes following operations. A substrate including a silicon (Si) layer is received. An amorphous germanium (Ge) layer is formed on the Si layer. A barrier layer is formed over the amorphous Ge layer. The substrate is annealed to transform the Si layer and the Ge layer to form a single crystalline SiGe layer. A Ge concentration is in a positive correlation with a ratio of a thickness of the Ge layer and a thickness of the Si layer.

公开(公告)号：US11712778B2

公开(公告)日：2023-08-01

申请号：US16550061

申请日：2019-08-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung-Kai Chen ,  Shang-Yu Wang ,  Wan-Chun Pan ,  Zink Wei ,  Hui-Chi Huang ,  Kei-Wei Chen

IPC: B24B49/12 ,  G01N21/64 ,  B24B53/017 ,  B24B37/20 ,  B24B37/12

CPC classification number: B24B49/12 ,  B24B37/12 ,  B24B37/20 ,  B24B53/017 ,  G01N21/6456

Abstract: A method of operating a chemical mechanical planarization (CMP) tool includes attaching a polishing pad to a first surface of a platen of the CMP tool using a glue; removing the polishing pad from the platen, wherein after removing the polishing pad, residue portions of the glue remain on the first surface of the platen; identifying locations of the residue portions of the glue on the first surface of the platen using a fluorescent material; and removing the residue portions of the glue from the first surface of the platen.