公开(公告)号：US10573749B2

公开(公告)日：2020-02-25

申请号：US15054089

申请日：2016-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Ziwei Fang ,  Shiu-Ko JangJian ,  Kei-Wei Chen ,  Huai-Tei Yang ,  Ying-Lang Wang

IPC: H01L27/01 ,  H01L29/78 ,  H01L27/12 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, first spacers, second spacers and source and drain regions is described. The substrate has fins and insulators disposed between the fins. The at least one gate structure is disposed over the fins and disposed on the insulators. The first spacers are disposed on opposite sidewalls of the at least one gate structure. The source and drain regions are disposed on two opposite sides of the at least one gate structure and beside the first spacers. The second spacers are disposed on the two opposite sides of the at least one gate structure and beside the first spacers. The source and drain regions are sandwiched between the opposite second spacers.

公开(公告)号：US10201887B2

公开(公告)日：2019-02-12

申请号：US15473967

申请日：2017-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hung Chen ,  Kei-Wei Chen

IPC: B24B37/26 ,  B24B37/22 ,  B24B37/04 ,  H01L21/67 ,  H01L21/683

Abstract: A polishing pad is provided. The polishing pad includes a base layer, a top layer, and multiple grooves. The top layer is located over the base layer and has a polishing surface and a bottom surface opposite to each other. The bottom surface is connected to the base layer. The grooves are formed on the bottom surface of the top layer.

公开(公告)号：US20180366585A1

公开(公告)日：2018-12-20

申请号：US16112766

申请日：2018-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Ziwei Fang ,  Kei-Wei Chen ,  Huai-Tei Yang

IPC: H01L29/78 ,  H01L21/223 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/7848 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/785

Abstract: A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm3 within a depth range of about 0-5 nm from a surface of the strained layer.

公开(公告)号：US09991384B2

公开(公告)日：2018-06-05

申请号：US14714242

申请日：2015-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun Hsiung Tsai ,  Kei-Wei Chen

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/267 ,  H01L29/423 ,  H01L29/66 ,  H01L21/306 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/306 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7847 ,  H01L29/7851

Abstract: A semiconductor Fin FET device includes a fin structure disposed over a substrate. The fin structure includes a channel layer. The Fin FET device also includes a gate structure including a gate electrode layer and a gate dielectric layer, covering a portion of the fin structure. Side-wall insulating layers are disposed over both main sides of the gate electrode layer. The Fin FET device includes a source and a drain, each including a stressor layer disposed in a recess formed by removing the fin structure not covered by the gate structure. The stressor layer includes a first to a third stressor layer formed in this order. In the source, an interface between the first stressor layer and the channel layer is located under one of the side-wall insulating layers closer to the source or the gate electrode.

公开(公告)号：US09722081B1

公开(公告)日：2017-08-01

申请号：US15009834

申请日：2016-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Ziwei Fang ,  Kei-Wei Chen ,  Huai-Tei Yang

IPC: H01L21/4763 ,  H01L29/78 ,  H01L21/265 ,  H01L21/223 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/7834 ,  H01L29/785

Abstract: A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm3 within a depth range of about 0-5 nm from a surface of the strained layer.

公开(公告)号：US12224179B2

公开(公告)日：2025-02-11

申请号：US18184438

申请日：2023-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Sheng Lin ,  Chi-Jen Liu ,  Chi-Hsiang Shen ,  Te-Ming Kung ,  Chun-Wei Hsu ,  Chia-Wei Ho ,  Yang-Chun Cheng ,  William Weilun Hong ,  Liang-Guang Chen ,  Kei-Wei Chen

IPC: H01L21/321 ,  C09G1/02 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535

Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

公开(公告)号：US20240395562A1

公开(公告)日：2024-11-28

申请号：US18790908

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Kung ,  Tung-Kai Chen ,  Chih-Chieh Chang ,  Kao-Feng Liao ,  Hui-Chi Huang ,  Kei-Wei Chen

IPC: H01L21/321 ,  C09G1/02 ,  C09G1/04 ,  H01L21/306 ,  H01L21/768

Abstract: Methods of manufacturing a chemical-mechanical polishing (CMP) slurry and methods of performing CMP process on a substrate comprising metal features are described herein. The CMP slurry may be manufactured using a balanced concentration ratio of chelator additives to inhibitor additives, the ratio being determined based on an electro potential (Ev) value of a metal material of the substrate. The CMP process may be performed on the substrate based on the balanced concentration ratio of chelator additives to inhibitor additives of the CMP slurry.

公开(公告)号：US12132107B2

公开(公告)日：2024-10-29

申请号：US17734687

申请日：2022-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsiung Tsai ,  Kuo-Feng Yu ,  Kei-Wei Chen

IPC: H01L29/78 ,  H01L21/223 ,  H01L21/225 ,  H01L21/3115 ,  H01L21/324 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L29/7834 ,  H01L21/2236 ,  H01L21/2254 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66492 ,  H01L29/66803

Abstract: A semiconductor structure includes a substrate, a first semiconductor fin, a second semiconductor fin, and a first lightly-doped drain (LDD) region. The first semiconductor fin is disposed on the substrate. The first semiconductor fin has a top surface and sidewalls. The second semiconductor fin is disposed on the substrate. The first semiconductor fin and the second semiconductor fin are separated from each other at a nanoscale distance. The first lightly-doped drain (LDD) region is disposed at least in the top surface and the sidewalls of the first semiconductor fin.

公开(公告)号：US12087590B2

公开(公告)日：2024-09-10

申请号：US18066934

申请日：2022-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Kung ,  Hui-Chi Huang ,  Kei-Wei Chen ,  Yen-Ting Chen

IPC: H01L21/306 ,  B24B37/24 ,  H01L21/321

CPC classification number: H01L21/30625 ,  B24B37/24 ,  H01L21/3212

Abstract: Provided herein are polishing pads in which microcapsules that include a polymer material and are dispersed, as well as methods of making and using the same. Such microcapsules are configured to break open (e.g., when the polishing pad is damaged during the dressing process), which releases the polymer material. When contacted with ultraviolet light the polymer material at least partially cures, healing the damage to the polishing pad. Such polishing pads have a longer lifetime and a more stable remove rate when compared to standard polishing pads.

公开(公告)号：US12030159B2

公开(公告)日：2024-07-09

申请号：US18334526

申请日：2023-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Kai Chen ,  Shang-Yu Wang ,  Wan-Chun Pan ,  Zink Wei ,  Hui-Chi Huang ,  Kei-Wei Chen

IPC: B24B49/12 ,  B24B37/12 ,  B24B37/20 ,  B24B53/017 ,  G01N21/64

CPC classification number: B24B49/12 ,  B24B37/12 ,  B24B37/20 ,  B24B53/017 ,  G01N21/6456

Abstract: A method of operating a chemical mechanical planarization (CMP) tool includes attaching a polishing pad to a first surface of a platen of the CMP tool using a glue; removing the polishing pad from the platen, wherein after removing the polishing pad, residue portions of the glue remain on the first surface of the platen; identifying locations of the residue portions of the glue on the first surface of the platen using a fluorescent material; and removing the residue portions of the glue from the first surface of the platen.