公开(公告)号：US11637021B2

公开(公告)日：2023-04-25

申请号：US17323951

申请日：2021-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Sheng Lin ,  Chi-Jen Liu ,  Chi-Hsiang Shen ,  Te-Ming Kung ,  Chun-Wei Hsu ,  Chia-Wei Ho ,  Yang-Chun Cheng ,  William Weilun Hong ,  Liang-Guang Chen ,  Kei-Wei Chen

IPC: H01L21/321 ,  H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  C09G1/02

Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

公开(公告)号：US11037799B2

公开(公告)日：2021-06-15

申请号：US16400620

申请日：2019-05-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Sheng Lin ,  Chi-Jen Liu ,  Kei-Wei Chen ,  Liang-Guang Chen ,  Te-Ming Kung ,  William Weilun Hong ,  Chi-Hsiang Shen ,  Chia-Wei Ho ,  Chun-Wei Hsu ,  Yang-Chun Cheng

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/321 ,  H01L21/768 ,  C09G1/02

Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

公开(公告)号：US20200098591A1

公开(公告)日：2020-03-26

申请号：US16400620

申请日：2019-05-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Sheng Lin ,  Chi-Jen Liu ,  Kei-Wei Chen ,  Liang-Guang Chen ,  Te-Ming Kung ,  William Weilun Hong ,  Chi-Hsiang Shen ,  Chia-Wei Ho ,  Chun-Wei Hsu ,  Yang-Chun Cheng

IPC: H01L21/321 ,  H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

公开(公告)号：US09595450B2

公开(公告)日：2017-03-14

申请号：US14141028

申请日：2013-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Hao Tu ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L27/088 ,  H01L21/3105 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L21/31055 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/66545

Abstract: A method of forming an integrated circuit device includes forming dummy gates over a semiconductor substrate, depositing a first dielectric layer over the dummy gates, chemical mechanical polishing to recede the first dielectric layer to the height of the dummy gates, etching to recess the first dielectric layer below the height of the gates, depositing one or more additional dielectric layers over the first dielectric layer, and chemical mechanical polishing to recede the one or more additional dielectric layers to the height of the gates. The method provides integrated circuit devices having metal gate electrodes and an inter-level dielectric at the gate level that includes a capping layer. The capping layer resists etching and preserves the gate height through a replacement gate process.

Abstract translation: 形成集成电路器件的方法包括在半导体衬底上形成伪栅极，在虚拟栅极上沉积第一介电层，化学机械抛光以将第一介电层退回到虚拟栅极的高度，蚀刻以使第一电介质 在栅极的高度以下，在第一介电层上沉积一个或多个附加电介质层，以及化学机械抛光以将一个或多个另外的介电层退回到栅极的高度。 该方法提供了集成电路器件，其具有金属栅极电极和栅极电平处的包括封盖层的级间电介质。 封盖层抵抗蚀刻并通过替换浇口工艺保持浇口高度。

公开(公告)号：US12224179B2

公开(公告)日：2025-02-11

申请号：US18184438

申请日：2023-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Sheng Lin ,  Chi-Jen Liu ,  Chi-Hsiang Shen ,  Te-Ming Kung ,  Chun-Wei Hsu ,  Chia-Wei Ho ,  Yang-Chun Cheng ,  William Weilun Hong ,  Liang-Guang Chen ,  Kei-Wei Chen

IPC: H01L21/321 ,  C09G1/02 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535

Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

公开(公告)号：US20240387187A1

公开(公告)日：2024-11-21

申请号：US18787026

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Chun Pan ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/3105 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/84

Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.

公开(公告)号：US20220012400A1

公开(公告)日：2022-01-13

申请号：US16926026

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Shuo Liu ,  Chih-Chun Hsia ,  Hsin Ting Chou ,  Kuanhua Su ,  William Weilun Hong ,  Chih Hung Chen ,  Kei-Wei Chen

IPC: G06F30/392 ,  G06T7/00

Abstract: A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.

公开(公告)号：US20200098590A1

公开(公告)日：2020-03-26

申请号：US16138806

申请日：2018-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Wei Hsu ,  Chi-Jen Liu ,  Kei-Wei Chen ,  Liang-Guang Chen ,  William Weilun Hong ,  Chi-hsiang Shen ,  Chia-Wei Ho ,  Yang-chun Cheng

IPC: H01L21/321 ,  H01L21/768 ,  C09G1/02

Abstract: The current disclosure describes a metal surface chemical mechanical polishing technique. A complex agent or micelle is included in the metal CMP slurry. The complex agent bonds with the oxidizer contained in the CMP slurry to form a complex, e.g., a supramolecular assembly, with an oxidizer molecule in the core of the assembly and surrounded by the complex agent molecule(s). The formed complexes have an enlarged size.

公开(公告)号：US20170256414A1

公开(公告)日：2017-09-07

申请号：US15058956

申请日：2016-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wen Liu ,  Che-Hao Tu ,  Po-Chin Nien ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/306 ,  H01L23/544 ,  H01L21/67 ,  H01L21/66

CPC classification number: H01L21/30625 ,  B24B37/30 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/67092 ,  H01L22/12 ,  H01L22/26 ,  H01L23/544 ,  H01L2223/54493

Abstract: A method includes measuring a topography of a wafer, determining that a first portion of the wafer has a greater thickness than a specified thickness. The method further includes, after measuring the wafer, performing a Chemical Mechanical Polishing (CMP) process to a first side of the wafer, and during application of the CMP process, applying additional pressure to a region of the wafer, the region comprising an asymmetric part of the wafer, the region including at least a part of the first portion of the wafer.

公开(公告)号：US20170213743A1

公开(公告)日：2017-07-27

申请号：US15182291

申请日：2016-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Chun Pan ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/3105 ,  H01L21/02

CPC classification number: H01L21/31051 ,  H01L21/02164 ,  H01L21/02205 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/02343 ,  H01L21/3105 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845

Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.