公开(公告)号：US20060282581A1

公开(公告)日：2006-12-14

申请号：US11505837

申请日：2006-08-18

Applicant: Yoshihiro Takemae

Inventor： Yoshihiro Takemae

IPC: G06F13/38

CPC classification number: G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0688 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0623 ,  G06F13/1694 ,  G06F2212/7201 ,  G11C5/04 ,  G11C7/1072

Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

公开(公告)号：US20050242864A1

公开(公告)日：2005-11-03

申请号：US11055784

申请日：2005-02-11

Applicant: Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

Inventor： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

IPC: G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  H03H11/26 ,  H03K5/00 ,  H03K5/13 ,  H03L7/081

CPC classification number: G11C7/106 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/002 ,  G11C2207/108 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/0805 ,  H03L7/0814

Abstract: Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.

Abstract translation: 公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。 该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路 输出定时，使得输出信号相对于外部时钟呈现给定的相位。 输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制 电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

公开(公告)号：US20050157585A1

公开(公告)日：2005-07-21

申请号：US10853313

申请日：2004-05-26

Applicant: Yoshiharu Kato ,  Gen Tsukishiro ,  Yoshihiro Takemae

Inventor： Yoshiharu Kato ,  Gen Tsukishiro ,  Yoshihiro Takemae

IPC: G06F12/00 ,  G06F12/02 ,  G06F13/42 ,  G11C8/00 ,  G11C11/406

CPC classification number: G06F13/4243 ,  G11C11/406 ,  Y02D10/14 ,  Y02D10/151

Abstract: It is intended to provide a memory control device and memory control method capable of reducing charge/discharge current consumed while various commands are inputted to a semiconductor memory device and reducing occurrence of power noises. During periods TT1, TT2, and TT3 which are parts of a period tCKE in which a clock enable signal CKE is in active state, supply of a control clock SD_CLK from a memory control device 1 to a synchronous-type semiconductor memory device 12 can be stopped. Furthermore, in case an input of a data input/output period of an external command and that of refresh operation period of a refresh command RCMD overlap and an access region of the external command and that of the refresh command RCMD do not coincide, those commands are converted to control command signal SD_CMD in parallel, whereby parallel conversion processing operation can be conducted.

Abstract translation: 旨在提供一种存储器控制装置和存储器控制方法，其能够在将各种命令输入到半导体存储器件中时减少所消耗的充电/放电电流并减少电力噪声的发生。 在时钟使能信号CKE处于活动状态的周期tCKE的一部分的时段TT 1，TT 2和TT 3期间，将控制时钟SD_CLK从存储器控制装置1提供给同步型半导体存储器件 12可以停止。 此外，在外部命令的数据输入/输出周期的输入和刷新命令RCMD的刷新操作周期的输入与外部命令的访问区域和刷新命令RCMD的访问区域不重合的情况下，这些命令 被并行地转换为控制指令信号SD_CMD，由此可以进行并行转换处理操作。

公开(公告)号：US06720804B2

公开(公告)日：2004-04-13

申请号：US10277986

申请日：2002-10-23

Applicant: Masao Taguchi ,  Yoshihiro Takemae

Inventor： Masao Taguchi ,  Yoshihiro Takemae

IPC: H03B100

CPC classification number: H03K19/018585

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

公开(公告)号：US06397312B1

公开(公告)日：2002-05-28

申请号：US08970086

申请日：1997-11-13

Applicant: Masao Nakano ,  Hiroyoshi Tomita ,  Kotoku Sato ,  Yoshihiro Takemae ,  Masao Taguchi

Inventor： Masao Nakano ,  Hiroyoshi Tomita ,  Kotoku Sato ,  Yoshihiro Takemae ,  Masao Taguchi

IPC: G06F1200

CPC classification number: G06F13/4243

Abstract: A memory system having a simple configuration capable of high-speed data transmission is disclosed. Data is output from a controller or a memory in synchronism with a clock or a data strobe signal. The clock or the data strobe signal is transmitted by a clock signal line or a data strobe signal line, respectively, arranged in parallel to a data signal line. A delay circuit delays by a predetermined time the signals transmitted through the clock signal line or the data strobe signal line. The clock or the data strobe signal thus assumes a phase suitable for retrieval at the destination, so that the data signal can be retrieved directly by means of the received clock or the received data strobe signal.

Abstract translation: 公开了一种具有能够进行高速数据传输的简单配置的存储器系统。 与时钟或数据选通信号同步地从控制器或存储器输出数据。 时钟或数据选通信号分别通过与数据信号线并联布置的时钟信号线或数据选通信号线来发送。 延迟电路在预定时间内延迟通过时钟信号线或数据选通信号线发送的信号。 因此，时钟或数据选通信号采取适合在目的地检索的相位，使得可以通过接收的时钟或接收的数据选通信号直接检索数据信号。

公开(公告)号：US06349068B2

公开(公告)日：2002-02-19

申请号：US09828847

申请日：2001-04-10

Applicant: Yoshihiro Takemae ,  Yasurou Matsuzaki

Inventor： Yoshihiro Takemae ,  Yasurou Matsuzaki

IPC: G11C700

CPC classification number: G11C11/40622 ,  G11C11/406

Abstract: A semiconductor memory device, which refreshes memory cells to retain data, has a first refresh mode and a second refresh mode. The first refresh mode is a mode for refreshing all of the memory cells, and the second refresh mode is a mode for refreshing a part of the memory cells. By refreshing only designated areas where data must be retained, power consumption in a refresh operation can be reduced, drastically cutting power consumption in a power-down mode.

Abstract translation: 刷新存储单元以保留数据的半导体存储器件具有第一刷新模式和第二刷新模式。 第一刷新模式是用于刷新所有存储单元的模式，第二刷新模式是用于刷新存储单元的一部分的模式。 通过仅刷新必须保留数据的指定区域，可以减少刷新操作中的功耗，从而在掉电模式下大幅度地削减功耗。

公开(公告)号：US6154405A

公开(公告)日：2000-11-28

申请号：US924315

申请日：1997-09-05

Applicant: Yoshihiro Takemae ,  Masao Taguchi ,  Masao Nakano ,  Hirohiko Mochizuki ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki ,  Tadao Aikawa

Inventor： Yoshihiro Takemae ,  Masao Taguchi ,  Masao Nakano ,  Hirohiko Mochizuki ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki ,  Tadao Aikawa

IPC: G11C11/409 ,  G11C7/10 ,  G11C7/12 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4096 ,  G11C7/02

CPC classification number: G11C11/4096 ,  G11C7/1048 ,  G11C7/12

Abstract: A semiconductor memory device includes memory cells, word lines connected to the memory cells, bit lines connected to the memory cells, and a first circuit which resets the bit lines to a reset potential which is based on data read in a previous read cycle.

Abstract translation: 半导体存储器件包括存储器单元，连接到存储器单元的字线，连接到存储器单元的位线，以及基于在先前读取周期中读取的数据将位线复位到复位电位的第一电路。

公开(公告)号：US6151274A

公开(公告)日：2000-11-21

申请号：US440665

申请日：1999-11-16

Applicant: Yoshihiro Takemae ,  Masao Taguchi ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Hirohiko Mochizuki ,  Atsushi Hatakeyama ,  Yoshinori Okajima

Inventor： Yoshihiro Takemae ,  Masao Taguchi ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Hirohiko Mochizuki ,  Atsushi Hatakeyama ,  Yoshinori Okajima

IPC: G06F13/42 ,  G06F1/10 ,  G06F1/12 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4093 ,  H03K5/00 ,  H03K5/13 ,  H03K5/135 ,  H03L7/00 ,  H03L7/081 ,  H04L7/00 ,  G11C8/00

CPC classification number: H03L7/0805 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/133 ,  H03K5/135 ,  H03L7/00 ,  H03L7/0814 ,  G11C2207/108

Abstract: A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state. In the case where the skew between the input signals is small as compared with the skew between the input signals and the clock, an input timing adjusting circuit is shared by a plurality of the input circuits.

Abstract translation: 公开了一种用于实现这种系统的系统和半导体器件。 该系统至少使用半导体器件来与外部时钟产生的内部时钟同步地检索输入信号，该输入信号与外部时钟同步地保持有效。 即使在时钟与接收端的信号之间产生相位差的情况下，或者即使在时钟输入电路与接收端的半导体装置中的其他信号输入电路之间产生相位差的情况下，数据 可以高速转移。 在接收端的半导体器件的每个输入电路包括输入定时调整电路，用于调节施加到输入电路的时钟的相位，使得输入电路以有效和稳定的状态检索输入信号。 在输入信号与输入信号和时钟之间的偏差相比较小的情况下，输入定时调整电路被多个输入电路共享。

公开(公告)号：US6028816A

公开(公告)日：2000-02-22

申请号：US924705

申请日：1997-09-05

Applicant: Yoshihiro Takemae ,  Masao Taguchi ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Hirohiko Mochizuki ,  Atsushi Hatakeyama ,  Yoshinori Okajima ,  Masao Nakano

Inventor： Yoshihiro Takemae ,  Masao Taguchi ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Hirohiko Mochizuki ,  Atsushi Hatakeyama ,  Yoshinori Okajima ,  Masao Nakano

IPC: G06F13/42 ,  G06F1/10 ,  G06F1/12 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4093 ,  H03K5/00 ,  H03K5/13 ,  H03K5/135 ,  H03L7/00 ,  H03L7/081 ,  H04L7/00 ,  G11C8/00

CPC classification number: H03L7/0805 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/133 ,  H03K5/135 ,  H03L7/00 ,  H03L7/0814 ,  G11C2207/108

Abstract: A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state. In the case where the skew between the input signals is small as compared with the skew between the input signals and the clock, an input timing adjusting circuit is shared by a plurality of the input circuits.

公开(公告)号：US5594699A

公开(公告)日：1997-01-14

申请号：US308105

申请日：1994-09-16

Applicant: Yukihiro Nomura ,  Yasuharu Satoh ,  Yoshihiro Takemae ,  Takaaki Furuyama ,  Mitsuhiro Nagao ,  Masahiro Niimi

Inventor： Yukihiro Nomura ,  Yasuharu Satoh ,  Yoshihiro Takemae ,  Takaaki Furuyama ,  Mitsuhiro Nagao ,  Masahiro Niimi

IPC: G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C7/00

CPC classification number: G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C5/143

Abstract: A DRAM (Dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

Abstract translation: 具有多个存储单元的DRAM（动态随机存取存储器）包括数据读/写电路读取或写入存储单元的数据，自刷新电路刷新存储在存储单元中的数据，以及电源单元， 数据读/写电路和自刷新电路的电力，电力在正常操作模式下具有第一电压电平，在自刷新模式下具有第二电压电平，其中第二电压电平低于 第一电压电平。