公开(公告)号：US06836018B2

公开(公告)日：2004-12-28

申请号：US10304264

申请日：2002-11-25

申请人： Gu-Sung Kim ,  Dong-Hyeon Jang ,  Min-Young Son ,  Sa-Yoon Kang

发明人： Gu-Sung Kim ,  Dong-Hyeon Jang ,  Min-Young Son ,  Sa-Yoon Kang

IPC分类号： H01L2348

CPC分类号： H01L24/10 ,  H01L23/3157 ,  H01L23/34 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K1/0271 ,  H05K3/3436 ,  H01L2924/00

摘要： A thermal-stress-absorbing interface structure is provided between a semiconductor integrated circuit chip and a surface-mount structure. The interface structure comprises an elongated conductive-bump pad having a first length-wise end and a second length-wise end, and a side. The pad has an interconnection line extending from the side thereof intermediate the first and the second ends. The interconnection line is electrically connected to the chip. The interface structure further includes a first polymer layer having an exposed surface, and a second polymer layer, each having a different modulus of elasticity, disposed below the pad. The second polymer layer extends over substantially the entire exposed surface of the first polymer layer to absorb a thermal stress during thermal cycling.

摘要翻译： 在半导体集成电路芯片和表面安装结构之间提供热应力吸收界面结构。 界面结构包括具有第一纵向端和第二纵向端以及侧面的细长导电凸块垫。 垫具有从第一端和第二端的中间的一侧延伸的互连线。 互连线电连接到芯片。 界面结构还包括设置在垫下方的具有暴露表面的第一聚合物层和每个具有不同弹性模量的第二聚合物层。 第二聚合物层在第一聚合物层的基本上整个暴露的表面上延伸以在热循环期间吸收热应力。

公开(公告)号：US06818998B2

公开(公告)日：2004-11-16

申请号：US10157272

申请日：2002-05-28

申请人： Yong Hwan Kwon ,  Se Yong Oh ,  Sa Yoon Kang

发明人： Yong Hwan Kwon ,  Se Yong Oh ,  Sa Yoon Kang

IPC分类号： H01L2334

CPC分类号： H01L23/3121 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked chip package includes a substrate having an upper surface and a lower surface, a first semiconductor chip having an upper surface and a lower surface, wherein the lower surface of the first semiconductor chip is attached to the upper surface of the substrate and the upper surface of the first semiconductor chip includes a plurality of first electrode pads, and a second semiconductor chip having an upper surface and a lower surface. The lower surface of the second semiconductor chip is attached to the upper surface of the first semiconductor chip, and the lower surface of the second semiconductor chip includes trenches that correspond to the locations of the first electrode pads on the upper surface of the first semiconductor chip.

摘要翻译： 堆叠式芯片封装包括具有上表面和下表面的基板，具有上表面和下表面的第一半导体芯片，其中第一半导体芯片的下表面附着到基板的上表面，上表面 第一半导体芯片的表面包括多个第一电极焊盘和具有上表面和下表面的第二半导体芯片。 第二半导体芯片的下表面附接到第一半导体芯片的上表面，并且第二半导体芯片的下表面包括对应于第一半导体芯片的上表面上的第一电极焊盘的位置的沟槽 。

公开(公告)号：US06717272B2

公开(公告)日：2004-04-06

申请号：US10376110

申请日：2003-02-26

申请人： Jin-Hyuk Lee ,  Sa-Yoon Kang ,  Dong-Whee Kwon ,  Ji-Yong You ,  Hye-Soo Shin

发明人： Jin-Hyuk Lee ,  Sa-Yoon Kang ,  Dong-Whee Kwon ,  Ji-Yong You ,  Hye-Soo Shin

IPC分类号： H01L2352

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05001 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45144 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device for reinforcing a substructure of a bond pad and a method for fabricating the same are provided. According to an embodiment, a semiconductor device for reinforcing a substructure of a bond pad comprises a semiconductor substrate and a substructure formed on the semiconductor substrate. The semiconductor device further includes an interlevel dielectric layer formed on the substructure. The interlevel dielectric layer includes a contact opening formed therein. The contact opening comprises a plurality of separate dots connected to each other. A contact plug is formed in the contact opening.

摘要翻译： 提供一种用于加强接合焊盘的子结构的半导体器件及其制造方法。 根据实施例，用于加强接合焊盘的子结构的半导体器件包括形成在半导体衬底上的半导体衬底和子结构。 半导体器件还包括形成在子结构上的层间电介质层。 层间电介质层包括形成在其中的接触开口。 接触开口包括彼此连接的多个分开的点。 接触插塞形成在接触开口中。

公开(公告)号：US06586275B2

公开(公告)日：2003-07-01

申请号：US10103630

申请日：2002-03-20

申请人： Gu-Sung Kim ,  Dong-Hyeon Jang ,  Min-Young Son ,  Sa-Yoon Kang

发明人： Gu-Sung Kim ,  Dong-Hyeon Jang ,  Min-Young Son ,  Sa-Yoon Kang

IPC分类号： H01L2144

CPC分类号： H01L24/10 ,  H01L23/3157 ,  H01L23/34 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K1/0271 ,  H05K3/3436 ,  H01L2924/00

摘要： A thermal-stress-absorbing interface structure between a semiconductor integrated circuit chip and a surface-mount structure and a method for manufacturing the same. The thermal-stress-absorbing interface structure comprises an elongated conductive-bump pad having a first length-wise end and a second length-wise end, and a side. The thermal-stress-absorbing interface structure includes means for allowing the first end of the pad to move up when the second end of the pad moves down and alternately allowing the first end to move down when the second end moves up, upon thermal cycling. The means has a center axis and the up-and-down movements of the pad are balanced on the center axis. In accordance with this novel structure of the present invention, interconnection reliability such as solder joint reliability can be significantly improved.

摘要翻译： 半导体集成电路芯片和表面安装结构之间的热应力吸收界面结构及其制造方法。 热应力吸收界面结构包括具有第一纵向端和第二纵向端以及侧面的细长导电凸块焊盘。 所述热应力吸收界面结构包括当所述垫的第二端向下移动时允许所述垫的第一端向上移动的装置，并且当热循环时，当所述第二端向上移动时交替允许所述第一端向下移动。 该装置具有中心轴线，并且垫片的上下运动在中心轴线上平衡。根据本发明的这种新颖结构，可以显着提高诸如焊点可靠性之类的互连可靠性。

公开(公告)号：US06448661B1

公开(公告)日：2002-09-10

申请号：US10059932

申请日：2002-01-28

申请人： Hyeong-Seob Kim ,  Sa-Yoon Kang ,  Myung-Kee Chung ,  In-Ku Kang ,  Kwan-Jai Lee

发明人： Hyeong-Seob Kim ,  Sa-Yoon Kang ,  Myung-Kee Chung ,  In-Ku Kang ,  Kwan-Jai Lee

IPC分类号： H01L2348

CPC分类号： H01L24/83 ,  H01L23/481 ,  H01L24/29 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

摘要： A three-dimensional, multi-chip package with chip selection pads formed at the chip-level and a manufacturing method thereof are provided. The three-dimensional, multi-chip package is formed by stacking a number (N) of semiconductor integrated circuit chips. Each chip comprises an integrated circuit die, a chip selection terminal, (N−1) chip selection pads, an insulation layer, (N−1) metal wirings, upper connection terminals, lower connection terminals, and trench wirings. The chip selection terminal of each chip is separated from the chip selection of the other chips by the chip selection pads formed at the chip-level.

摘要翻译： 提供了一种具有在芯片级形成的芯片选择焊盘的三维多芯片封装及其制造方法。 通过堆叠多个（N）个半导体集成电路芯片来形成三维多芯片封装。 每个芯片包括集成电路管芯，芯片选择端子（N-1）芯片选择焊盘，绝缘层，（N-1）金属布线，上连接端子，下连接端子和沟槽布线。 每个芯片的芯片选择端通过在芯片级形成的芯片选择焊盘与其他芯片的芯片选择分离。

公开(公告)号：US5882932A

公开(公告)日：1999-03-16

申请号：US927562

申请日：1997-09-08

申请人： Kyung Shick Yoon ,  Yong Seok Park ,  Hyung Charn Kim ,  Yong Teak Yi ,  Yeal Soon Hwang ,  Sung Yoon Kang ,  Ki Nom Chung ,  Jin Cheol Kim

发明人： Kyung Shick Yoon ,  Yong Seok Park ,  Hyung Charn Kim ,  Yong Teak Yi ,  Yeal Soon Hwang ,  Sung Yoon Kang ,  Ki Nom Chung ,  Jin Cheol Kim

IPC分类号： C12Q1/06 ,  C12M1/36 ,  C12Q1/02 ,  G01N33/18

CPC分类号： G01N33/1866 ,  C12Q1/02 ,  G01N33/1806 ,  Y10T436/209163

摘要： A continuous, quick measurement method of BOD, and an apparatus therefor is disclosed. The apparatus comprises a sample tank in which a sample is prepared suitably for the measurement, a reactor in which microorganisms maintain their activity, a medium reservoir which contains nutrients for the growth of the microorganisms, pumps for transferring liquids, and a microprocessor which controls the operation of all means including a magnetic stirrer for mixing the liquid in the reactor and diagnoses of the apparatus itself. Using the apparatus, the method comprises a continuous culture stage, an endogenous respiration stage, a endogenous respiration rate-measuring stage, a sample feeding stage and a BODq measuring stage. The apparatus can detect BOD in one hour and is very low in error rate. Further, because microorganisms can be continuously cultured, the apparatus is semi-permanent, easy to manage, low in cost and suitable to be operated at a treatment site.

摘要翻译： 公开了一种连续，快速的BOD测量方法及其装置。 该装置包括样品罐，其中适当地制备样品用于测量，微生物维持其活性的反应器，包含用于生长微生物的营养物的介质储存器，用于转移液体的泵和控制所述微生物的微处理器 包括用于混合反应器中的液体的磁力搅拌器的所有装置的操作以及设备本身的诊断。 使用该装置，该方法包括连续培养阶段，内源性呼吸阶段，内源性呼吸速率测量阶段，样品进料阶段和BODq测量阶段。 该装置可以在一小时内检测到BOD，误差率非常低。 此外，由于可以连续培养微生物，所以该装置是半永久性的，易于管理，成本低廉并且适合于在治疗部位操作。

公开(公告)号：US08273311B2

公开(公告)日：2012-09-25

申请号：US12160242

申请日：2007-01-11

申请人： Kang Sun Lee ,  Ji Yoon Kang ,  Sung Shin Ryu ,  In Hye Lee ,  Choong Kim ,  Su Kyoung Chae ,  Jin Woo Lee

发明人： Kang Sun Lee ,  Ji Yoon Kang ,  Sung Shin Ryu ,  In Hye Lee ,  Choong Kim ,  Su Kyoung Chae ,  Jin Woo Lee

IPC分类号： B01D21/00

CPC分类号： B03C1/288 ,  B03C1/30

摘要： Disclosed is an apparatus and method for injecting liquid-drops of particle mixture liquid including a mixture of biological particles, affecting magnetic field, and having only positive particles, which are combined with magnetic responsive material, separated by magnetic force, and having negative particles, which are not combined with magnetic responsive material, precipitated by gravity.

摘要翻译： 本发明涉及一种装置和方法，用于将包括影响磁场的生物颗粒的混合物的粒子混合液体的液滴注入，并且仅具有正磁性颗粒，其与通过磁力分离并具有负性颗粒的磁响应材料组合， 其不与磁响应材料结合，由重力沉淀。

公开(公告)号：US20110143625A1

公开(公告)日：2011-06-16

申请号：US13033307

申请日：2011-02-23

申请人： Kyoung-sei Choi ,  Byung-seo Kim ,  Young-jae Joo ,  Ye-chung Chung ,  Kyong-soon Cho ,  Sang-heui Lee ,  Si-hoon Lee ,  Sa-yoon Kang ,  Dae-woo Son ,  Sang-gui Jo ,  Jeong-kyu Ha ,  Young-sang Cho

发明人： Kyoung-sei Choi ,  Byung-seo Kim ,  Young-jae Joo ,  Ye-chung Chung ,  Kyong-soon Cho ,  Sang-heui Lee ,  Si-hoon Lee ,  Sa-yoon Kang ,  Dae-woo Son ,  Sang-gui Jo ,  Jeong-kyu Ha ,  Young-sang Cho

IPC分类号： H01J9/00

CPC分类号： H01L23/49838 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01079 ,  H05K1/0203 ,  H05K1/189 ,  H05K2201/09109 ,  H05K2201/1028 ,  H05K2201/10674 ,  H05K2203/1581 ,  H01L2924/00

摘要： Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.

摘要翻译： 公开了一种片上胶片（COF）型半导体封装以及使用其的器件。 COF型半导体封装可以包括包括顶表面和底表面的绝缘衬底，绝缘衬底的顶表面上的半导体器件，绝缘衬底的底表面上的散热部件，以及绝缘衬底的至少一个空间 绝缘基板的底表面和散热部件的顶表面。

公开(公告)号：US20110119912A1

公开(公告)日：2011-05-26

申请号：US13019453

申请日：2011-02-02

申请人： Kyoung-Sei Choi ,  Sa-Yoon Kang ,  Yong-Hwan Kwon ,  Chung-Sun Lee

发明人： Kyoung-Sei Choi ,  Sa-Yoon Kang ,  Yong-Hwan Kwon ,  Chung-Sun Lee

IPC分类号： H05K3/00

CPC分类号： H05K3/28 ,  H05K1/036 ,  H05K1/0393 ,  H05K3/101 ,  H05K3/107 ,  H05K3/1258 ,  H05K2201/0129 ,  H05K2201/0162 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/0759 ,  H05K2203/1105 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/4916

摘要： A method for manufacturing a tape wiring board in accordance with the present invention may employ an imprinting process in forming a wiring pattern, thereby reducing the number of processes for manufacturing a tape wiring board and allowing the manufacturing process to proceed in a single production line. Therefore, the manufacturing time and cost may he reduced. A profile of the wiring pattern may be determined by the shape of an impression pattern of a mold. This may establish the top width of inner and outer leads and incorporate tine pad pitch. Although ILB and OLB process may use an NCP, connection reliability may be established due to the soft and elastic wiring pattern.

摘要翻译： 根据本发明的制造带布线板的方法可以在形成布线图案中采用压印工艺，从而减少了用于制造带布线板的工艺的数量，并允许制造工艺在单个生产线中进行。 因此，制造时间和成本可能会降低。 布线图案的轮廓可以通过模具的印模图案的形状来确定。 这可以建立内部和外部引线的顶部宽度并结合齿垫间距。 虽然ILB和OLB过程可能使用NCP，但是由于软和弹性布线图案可能建立连接可靠性。

公开(公告)号：US07948768B2

公开(公告)日：2011-05-24

申请号：US12584516

申请日：2009-09-08

申请人： Sang-Ho Park ,  Sa-Yoon Kang ,  Si-Hoon Lee

发明人： Sang-Ho Park ,  Sa-Yoon Kang ,  Si-Hoon Lee

IPC分类号： H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC分类号： H01L23/49838 ,  G02F1/13452 ,  H01L21/563 ,  H01L23/4985 ,  H01L2924/0002 ,  H01L2924/12044 ,  H05K1/142 ,  H05K1/147 ,  H05K3/361 ,  H05K2201/09227 ,  H05K2201/10681 ,  H01L2924/00

摘要： A tape circuit substrate includes a base film with first wiring and second wiring disposed on the base film. The first wiring extends into a chip mount portion through a first side and bends within the chip mount portion toward a second side. The second wiring extends into the chip mount portion through a third side and bends within the chip mount portion toward the second side. The first, second, and third sides are different sides of the chip mount portion. Thus, size and in turn cost of the base film are minimized by arranging wirings within the chip mount portion for further miniaturization of electronic devices, such as a display panel assembly, using the tape circuit substrate.

摘要翻译： 带状电路基板包括具有第一布线的基膜和设置在基膜上的第二布线。 第一布线通过第一侧延伸到芯片安装部分中，并且在芯片安装部分内向第二侧弯曲。 第二布线通过第三侧延伸到芯片安装部分，并且在芯片安装部分内向第二侧弯曲。 第一，第二和第三面是芯片安装部分的不同侧面。 因此，通过在芯片安装部分内布置布线以使得使用带电路基板的诸如显示面板组件的电子设备的进一步小型化来使基膜的尺寸和成本进一步降低。