公开(公告)号：US06818998B2

公开(公告)日：2004-11-16

申请号：US10157272

申请日：2002-05-28

申请人： Yong Hwan Kwon ,  Se Yong Oh ,  Sa Yoon Kang

发明人： Yong Hwan Kwon ,  Se Yong Oh ,  Sa Yoon Kang

IPC分类号： H01L2334

CPC分类号： H01L23/3121 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked chip package includes a substrate having an upper surface and a lower surface, a first semiconductor chip having an upper surface and a lower surface, wherein the lower surface of the first semiconductor chip is attached to the upper surface of the substrate and the upper surface of the first semiconductor chip includes a plurality of first electrode pads, and a second semiconductor chip having an upper surface and a lower surface. The lower surface of the second semiconductor chip is attached to the upper surface of the first semiconductor chip, and the lower surface of the second semiconductor chip includes trenches that correspond to the locations of the first electrode pads on the upper surface of the first semiconductor chip.

摘要翻译： 堆叠式芯片封装包括具有上表面和下表面的基板，具有上表面和下表面的第一半导体芯片，其中第一半导体芯片的下表面附着到基板的上表面，上表面 第一半导体芯片的表面包括多个第一电极焊盘和具有上表面和下表面的第二半导体芯片。 第二半导体芯片的下表面附接到第一半导体芯片的上表面，并且第二半导体芯片的下表面包括对应于第一半导体芯片的上表面上的第一电极焊盘的位置的沟槽 。

公开(公告)号：US07115483B2

公开(公告)日：2006-10-03

申请号：US10962591

申请日：2004-10-13

申请人： Yong Hwan Kwon ,  Se Yong Oh ,  Sa Yoon Kang

发明人： Yong Hwan Kwon ,  Se Yong Oh ,  Sa Yoon Kang

IPC分类号： H01L21/00 ,  H01L21/44 ,  H01L21/30 ,  H01L23/02

CPC分类号： H01L23/3121 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked chip package includes a substrate having an upper surface and a lower surface, a first semiconductor chip having an upper surface and a lower surface, wherein the lower surface of the first semiconductor chip is attached to the upper surface of the substrate and the upper surface of the first semiconductor chip includes a plurality of first electrode pads, and a second semiconductor chip having an upper surface and a lower surface. The lower surface of the second semiconductor chip is attached to the upper surface of the first semiconductor chip, and the lower surface of the second semiconductor chip includes trenches that correspond to the locations of the first electrode pads on the upper surface of the first semiconductor chip.

公开(公告)号：US06555921B2

公开(公告)日：2003-04-29

申请号：US09982338

申请日：2001-10-17

申请人： Yong Hwan Kwon ,  Sa Yoon Kang ,  Nam Seog Kim ,  Dong Hyeon Jang

发明人： Yong Hwan Kwon ,  Sa Yoon Kang ,  Nam Seog Kim ,  Dong Hyeon Jang

IPC分类号： H01L2348

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/02 ,  H01L24/12 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/11822 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A semiconductor package manufacturing method includes: providing a rerouting film; attaching a semiconductor wafer having integrated circuits to the rerouting film, such that chip pads of the integrated circuits correspond to via holes of the rerouting film; forming a solder filling in each of the via holes to electrically connect the chip pads to the metal pattern layer; forming external terminals on terminal pads of the rerouting film; and separating the wafer and the rerouting film into individual semiconductor packages. A method further includes forming a protection layer on the solder filling. Instead of the semiconductor wafer, individual integrated circuit chips can be attached on the rerouting film. The semiconductor package includes: an integrated circuit having chip pads; a substrate attached to the integrated circuit so that via holes of the substrate are above the chip pads; solder fillings inside the via holes, the solder fillings electrically connecting the chips pads to the pattern metal layer; and another dielectric layer between the substrate and the semiconductor integrated circuit. The semiconductor package further includes external terminals, interconnection bumps on the chip pads, and polymer protection layers on the solder fillings.

公开(公告)号：US06407459B2

公开(公告)日：2002-06-18

申请号：US09853950

申请日：2001-05-10

申请人： Yong Hwan Kwon ,  Sa Yoon Kang

发明人： Yong Hwan Kwon ,  Sa Yoon Kang

IPC分类号： H01L2144

CPC分类号： H01L24/94 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/97 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/02319 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/03003 ,  H01L2224/03438 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2224/02 ,  H01L2924/00 ,  H01L2224/03

摘要： A semiconductor package which includes: a semiconductor integrated circuit having chip pads formed thereon; interconnection bumps overlying on the chip pads; a patterned metal layer connecting to the interconnection bumps; a first dielectric layer under the patterned metal layer; a second dielectric layer overlying on the patterned metal layer; and terminal pads connecting to the patterned metal layer. The semiconductor package can further include external terminals connecting to the terminal pads, a third dielectric layer filling a gap between the first dielectric layer and the semiconductor integrated circuit.

摘要翻译： 一种半导体封装件，包括：其上形成有芯片焊盘的半导体集成电路; 互连凸块覆盖在芯片焊盘上; 连接到互连凸块的图案化金属层; 图案化金属层下面的第一介电层; 覆盖在图案化金属层上的第二电介质层; 以及连接到图案化金属层的端子焊盘。 半导体封装还可以包括连接到端子焊盘的外部端子，填充第一介电层和半导体集成电路之间的间隙的第三介电层。

公开(公告)号：US06376279B1

公开(公告)日：2002-04-23

申请号：US09482216

申请日：2000-01-12

申请人： Yong Hwan Kwon ,  Sa Yoon Kang ,  Nam Seog Kim ,  Dong Hyeon Jang

发明人： Yong Hwan Kwon ,  Sa Yoon Kang ,  Nam Seog Kim ,  Dong Hyeon Jang

IPC分类号： H01L2144

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/02 ,  H01L24/12 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/11822 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A semiconductor package manufacturing method includes: providing a rerouting film; attaching a semiconductor wafer having integrated circuits to the rerouting film, such that chip pads of the integrated circuits correspond to via holes of the rerouting film; forming a solder filling in each of the via holes to electrically connect the chip pads to the metal pattern layer; forming external terminals on terminal pads of the rerouting film; and separating the wafer and the rerouting film into individual semiconductor packages. A method further includes forming a protection layer on the solder filling. Instead of the semiconductor wafer, individual integrated circuit chips can be attached on the rerouting film. The semiconductor package includes: an integrated circuit having chip pads; a substrate attached to the integrated circuit so that via holes of the substrate are above the chip pads; solder fillings inside the via holes, the solder fillings electrically connecting the chips pads to the pattern metal layer; and another dielectric layer between the substrate and the semiconductor integrated circuit. The semiconductor package further includes external terminals, interconnection bumps on the chip pads, and polymer protection layers on the solder fillings.

摘要翻译： 半导体封装制造方法包括：提供重新布线膜; 将具有集成电路的半导体晶片连接到重新布线膜，使得集成电路的芯片焊盘对应于重新布线膜的通孔; 在每个所述通孔中形成焊料填充物，以将所述芯片焊盘电连接到所述金属图案层; 在重新布线膜的端子焊盘上形成外部端子; 以及将所述晶片和所述重新布线膜分离成单独的半导体封装。 一种方法还包括在焊料填充物上形成保护层。 代替半导体晶片，各个集成电路芯片可以附着在重新布线的薄膜上。 半导体封装包括：具有芯片焊盘的集成电路; 附着到集成电路的衬底，使得衬底的通孔位于芯片焊盘之上; 通孔内的焊料填充物，焊料填充物将芯片焊盘电连接到图案金属层; 以及衬底和半导体集成电路之间的另一介质层。 半导体封装还包括外部端子，芯片焊盘上的互连凸块和焊料填充物上的聚合物保护层。

公开(公告)号：US06235552B1

公开(公告)日：2001-05-22

申请号：US09482160

申请日：2000-01-12

申请人： Yong Hwan Kwon ,  Sa Yoon Kang

发明人： Yong Hwan Kwon ,  Sa Yoon Kang

IPC分类号： H01L2144

CPC分类号： H01L24/94 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/97 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/02319 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/03003 ,  H01L2224/03438 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2224/02 ,  H01L2924/00 ,  H01L2224/03

摘要： A method for manufacturing a chip scale package includes: providing a redistribution substrate; attaching a semiconductor wafer to the redistribution substrate; forming external terminals on the redistribution substrate; and separating the semiconductor wafer and the redistribution substrate into individual integrated circuits. The method can further include forming a buffer layer by filling a gap between the semiconductor wafer and the redistribution substrate with a dielectric material. Another method is the same as the method described above except that instead of the semiconductor wafer, individual integrated circuit chips attach to the redistribution substrate. Meanwhile, a semiconductor package includes: a semiconductor integrated circuit having chip pads formed thereon; interconnection bumps overlying on the chip pads; a patterned metal layer connecting to the interconnetion bumps; a first dielectric layer under the patterned metal layer; a second dielectric layer overlying on the patterned metal layer; and terminal pads connecting to the patterned metal layer. The semiconductor package can further include external terminals connecting to the terminal pads, a third dielectric layer filling a gap between the first dielectric layer and the semiconductor integrated circuit.

摘要翻译： 芯片级封装的制造方法包括：提供再分布基板; 将半导体晶片附接到再分布基板; 在再分布基板上形成外部端子; 以及将半导体晶片和再分配基板分离成单独的集成电路。 该方法还可以包括通过用介电材料填充半导体晶片和再分布基板之间的间隙来形成缓冲层。 另一方法与上述方法相同，除了代替半导体晶片，各个集成电路芯片附着到再分布基板。 同时，半导体封装包括：其上形成有芯片焊盘的半导体集成电路; 互连凸块覆盖在芯片焊盘上; 连接到互连凸块的图案化金属层; 图案化金属层下面的第一介电层; 覆盖在图案化金属层上的第二电介质层; 以及连接到图案化金属层的端子焊盘。 半导体封装还可以包括连接到端子焊盘的外部端子，填充第一介电层和半导体集成电路之间的间隙的第三介电层。

公开(公告)号：US06607938B2

公开(公告)日：2003-08-19

申请号：US10200077

申请日：2002-07-18

申请人： Yong Hwan Kwon ,  Sa Yoon Kang ,  Dong Hyeon Jang ,  Min Kyo Cho ,  Gu Sung Kim

发明人： Yong Hwan Kwon ,  Sa Yoon Kang ,  Dong Hyeon Jang ,  Min Kyo Cho ,  Gu Sung Kim

IPC分类号： H01L2144

CPC分类号： H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/013

摘要： A wafer level chip package has a redistrubution substrate, at least one lower semiconductor chip stacked on the redisctribution substrate, and an uppermost semiconductor chip. The redistribution substrate has a redistribution layer and substrate pads connected to the redistribution layer. The lower semiconductor chip is stacked on the redistribution layer and may have through holes for partially exposing the redistribution layer, the through holes corresponding to the substrate pads, and having conductive filling material filling the through holes. The uppermost semiconductor chip may have the same elements as the lower semiconductor chip, and may be flip chip bonded to the through holes. The package may further have a filling layer for filling areas between chips, a metal lid for coating most of the external surfaces, and external connection terminals formed on and electrically connected to the exposed redistribution layer from the first dielectric layer of the redistribution substrate.

公开(公告)号：US08338868B2

公开(公告)日：2012-12-25

申请号：US12626343

申请日：2009-11-25

申请人： Bong Ki Mheen ,  Albert J. P. Theuwissen ,  Jae Sik Sim ,  Mi Ran Park ,  Yong Hwan Kwon ,  Eun Soo Nam

发明人： Bong Ki Mheen ,  Albert J. P. Theuwissen ,  Jae Sik Sim ,  Mi Ran Park ,  Yong Hwan Kwon ,  Eun Soo Nam

IPC分类号： H01L31/062 ,  H01L31/113

CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14641

摘要： An image sensor with a shared photodiode is provided. The image sensor includes at least two unit pixels, each of which includes a photodiode, a diffusion region which gathers electrons from the photodiode, a transfer transistor which connects the photodiode with the diffusion region, and a readout circuit which reads out a signal from the diffusion region. Photodiodes of neighboring unit pixels are disposed symmetrically to be adjacent to one another to form a shared photodiode. The image sensor does not have a STI region which causes a dark current restricting its performance and does not require a basic minimum design factor (a distance or an area) related to a STI region. A region corresponding to a STI region may be used as a region of a photodiode or for additional pixel scaling. Therefore, a limitation in scaling of a photodiode is overcome, and pixel performance is improved in spite of pixel scaling.

摘要翻译： 提供具有共享光电二极管的图像传感器。 图像传感器包括至少两个单位像素，每个单元像素包括光电二极管，从光电二极管收集电子的扩散区域，连接光电二极管与扩散区域的传输晶体管，以及读出电路， 扩散区。 相邻单位像素的光电二极管彼此对称设置以形成共用光电二极管。 图像传感器不具有导致暗电流限制其性能的STI区域，并且不需要与STI区域相关的基本最小设计因子（距离或面积）。 可以将对应于STI区域的区域用作光电二极管的区域或用于附加像素缩放。 因此，克服了光电二极管的缩放的限制，并且尽管像素缩放来提高像素性能。

公开(公告)号：US08335200B2

公开(公告)日：2012-12-18

申请号：US12676749

申请日：2008-05-23

申请人： Yong Duck Chung ,  Kwang Seong Choi ,  Jae Sik Sim ,  Yong Hwan Kwon ,  Sung Bok Kim ,  Je Ha Kim

发明人： Yong Duck Chung ,  Kwang Seong Choi ,  Jae Sik Sim ,  Yong Hwan Kwon ,  Sung Bok Kim ,  Je Ha Kim

IPC分类号： H04H1/00

CPC分类号： H04B10/25759 ,  H04W88/10

摘要： Provided are a method and device for separating and converting multiband signals. The device includes a photoelectric converter for converting an externally received optical signal into an electrical signal, a first switch for separating the converted electrical signal into signals according to frequency bands, a first mobile communication band-pass amplifier for amplifying a mobile communication network signal of the signals separated by the first switch, a broadband up-converter for up-converting a baseband signal of the signals separated by the first switch into a broadband signal, a first broadband amplifier for amplifying the broadband signal output from the broadband up-converter, and a transmitter for wirelessly transmitting the signals amplified by the first mobile communication band-pass amplifier and the first broadband amplifier.

摘要翻译： 提供了用于分离和转换多频带信号的方法和装置。 该装置包括用于将外部接收的光信号转换为电信号的光电转换器，用于根据频带将转换后的电信号分离为信号的第一开关，用于放大移动通信网络信号的第一移动通信带通放大器 由第一开关分离的信号，用于将由第一开关分离的信号的基带信号上变频为宽带信号的宽带上变频器，用于放大从宽带上变频器输出的宽带信号的第一宽带放大器， 以及用于无线地发送由第一移动通信带通放大器和第一宽带放大器放大的信号的发射机。

公开(公告)号：US20100320500A1

公开(公告)日：2010-12-23

申请号：US12870998

申请日：2010-08-30

申请人： UN BYOUNG KANG ,  Yong Hwan Kwon ,  Chung Sun Lee ,  Woon Seong Kwon ,  Hyung Sun Jang

发明人： UN BYOUNG KANG ,  Yong Hwan Kwon ,  Chung Sun Lee ,  Woon Seong Kwon ,  Hyung Sun Jang

IPC分类号： H01L27/15 ,  H01L23/52 ,  H01L21/336

CPC分类号： H01L24/83 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11901 ,  H01L2224/11912 ,  H01L2224/13099 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/01007 ,  H01L2924/01028 ,  H01L2224/29099 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device includes forming a diffusion barrier layer on a substrate, and forming at least two features on the substrate such that the diffusion barrier layer is respectively disposed between each feature and the substrate and contacts the at least two features. A first impurity region of the substrate contains impurities of a first type, a second impurity region of the substrate contains impurities of a second type, different from the first type, a first feature of the at least two features is in the first impurity region, and a second feature of the at least two features is in the second impurity region, such that the second feature is electrically isolated from first feature by the different impurity regions.

摘要翻译： 一种制造半导体器件的方法包括在衬底上形成扩散阻挡层，并在衬底上形成至少两个特征，使得扩散阻挡层分别设置在每个特征和衬底之间，并接触至少两个特征。 衬底的第一杂质区包含第一类杂质，衬底的第二杂质区包含不同于第一类型的第二类杂质，所述至少两个特征的第一特征在第一杂质区， 并且所述至少两个特征的第二特征在于第二杂质区域，使得第二特征通过不同的杂质区域与第一特征电隔离。