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公开(公告)号：US11887681B2
公开(公告)日：2024-01-30
申请号：US17675477
申请日：2022-02-18
Applicant: Micron Technology, Inc.
Inventor： Vamsi Rayaprolu , Ashutosh Malshe , Gary Besinga , Roy Leonard
CPC classification number: G11C16/3495 , G11C16/102 , G11C16/16 , G11C16/26 , G11C16/32
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a data validity metric value with respect to a source set of memory cells of the memory device; determining whether the data validity metric value satisfies a first threshold criterion; responsive to determining that the data validity metric value satisfies the first threshold criterion, performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a second threshold criterion; and responsive to determining that the data integrity metric value fails to satisfy the second threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device.
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52.发明公开公开(公告)号：US20240021255A1
公开(公告)日：2024-01-18
申请号：US18356522
申请日：2023-07-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Myungnam Lee , Daehan Kim , Wontaeck Jung
CPC classification number: G11C16/3445 , G11C16/28 , G11C16/16 , G11C16/3409
Abstract: A method of detecting, by a nonvolatile memory system, a defective memory cell block from among memory cell blocks, includes performing, after performing an erase operation, a read operation on at least some memory cells included in a target memory cell block based on an off-cell detection voltage that is different from a read reference voltage that distinguishes an off-cell on which no data is written from an on-cell on which data is written; counting a number of hard off-cells having a higher threshold voltage than the off-cell detection voltage from among the memory cells based on a result of performing the read operation; and identifying whether the target memory cell block is a defective memory cell block based on the number of counted hard off-cells.
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公开(公告)号：US11869604B2
公开(公告)日：2024-01-09
申请号：US18103226
申请日：2023-01-30
Applicant: Micron Technology, Inc.
Inventor： Antonino Mondello , Alberto Troia
CPC classification number: G11C16/3445 , G11C16/16 , G11C16/28 , G11C16/349
Abstract: The present disclosure relates to a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, and a method for checking the erasing phase of the non-volatile device; the method comprises:
performing a dynamic erase operation of at least a memory block;
storing in a dummy row at least internal block variables of said dynamic erase operation and/or a known pattern.-
公开(公告)号：US11869590B2
公开(公告)日：2024-01-09
申请号：US17458954
申请日：2021-08-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Andrew Bicksler , Marc Aoulaiche
Abstract: A memory device includes a string of series-connected memory cells, a data line, a first select transistor, a common source, a second select transistor, and a gate leakage transistor. The string of series-connected memory cells includes a vertical channel region. Each memory cell of the string of series-connected memory cells includes a first gate stack structure. The data line is connected to the vertical channel region. The first select transistor is connected between the data line and the string of series-connected memory cells. The second select transistor is connected between the common source and the string of series-connected memory cells. The gate leakage transistor is connected between the first select transistor and the second select transistor. The gate leakage transistor includes a second gate stack structure different from the first gate stack structure.
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公开(公告)号：US11862263B2
公开(公告)日：2024-01-02
申请号：US17729048
申请日：2022-04-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sangsoo Cha , Suyong Jang
CPC classification number: G11C16/3495 , G11C16/16 , G11C16/26 , G11C29/72
Abstract: A method of operating a storage device including a non-volatile memory includes storing program and erase counts of the non-volatile memory as metadata in units of super blocks, wherein each of the super blocks includes a pre-defined number of blocks of the non-volatile memory, performing a read operation on a first block included in a first super block based on a first read level, storing the first read level as a history read level of the first super block in a history buffer when the read operation on the first block is successful, receiving a read request for a second block of the first super block and an address of the second block from a host, and performing a read operation on the second block based on the history read level stored in the history buffer. The pre-defined number is at least two.
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Patent Agency Ranking
公开(公告)号：US11862260B2
公开(公告)日：2024-01-02
申请号：US17671015
申请日：2022-02-14
Applicant: SanDisk Technologies LLC
Inventor： Jiacen Guo , Swaroop Kaza
CPC classification number: G11C16/349 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/3422 , H10B43/27
Abstract: Read disturb audit techniques that include algorithmically applying audit verify voltages to erased wordlines in an open memory block are described. In an audit verify technique, a pass-through voltage ensured to be higher than any threshold voltage of any cell is applied to each wordline in an open memory block that includes one or more programmed memory cells, and an audit verify voltage lower than the pass-through voltage is applied to each erased wordline. A first bit count representing a number of non-conductive bitline(s) is determined and compared to a threshold value to determine whether to continue or discontinue block operation. In an audit verify and audit gap technique, the erased wordlines are divided into disjoint first and second groups, and an audit verify voltage and a non-verify voltage are alternatively applied to the groups in different audit verify stages.
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公开(公告)号：US11862238B2
公开(公告)日：2024-01-02
申请号：US17941799
申请日：2022-09-09
Applicant: Micron Technology, Inc.
Inventor： Tomoharu Tanaka
IPC: G11C5/02 , G11C11/4096 , G11C16/16 , G06F13/16 , G11C11/4094
CPC classification number: G11C11/4096 , G06F13/1673 , G11C5/025 , G11C11/4094 , G11C16/16
Abstract: Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes a substrate, a first deck including first memory cell strings located over the substrate, a second deck including second memory cell strings and located over the first deck, first data lines located between the first and second decks and coupled to the first memory cell strings, second data lines located over the second deck and coupled to the second memory cell strings, and first and second circuitries. The first and second data lines extending in a direction from a first portion of the substrate to a second portion of the substrate. The first buffer circuitry is located in the first portion of the substrate under the first memory cell strings of the first deck and coupled to the first data lines. The second buffer circuitry is located in the second portion of the substrate under the first memory cell strings of the first deck and coupled to the second data lines.
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公开(公告)号：US20230402101A1
公开(公告)日：2023-12-14
申请号：US17835396
申请日：2022-06-08
Applicant: SanDisk Technologies LLC
Inventor： KIRUBAKARAN PERIYANNAN , DANIEL J. LINNEN , JAYAVEL PACHAMUTHU
CPC classification number: G11C16/102 , G11C16/16 , G11C16/26 , G11C16/08 , G11C16/24
Abstract: Embodiments of the present disclosure generally include methods of specially programming a set of memory cells, wherein each specially programmed memory cell is specially programmed along with programming a plurality of wordlines, and wherein each memory cell is specially programmed by altering a bitline and gate voltage applied to the memory cell. The methods further includes performing a sensing operation across a set of strings in the array of memory cells, determining, based on the sensing operation, whether one or more strings failed to conduct during a sensing operation, and determining the last programmed wordline using the one or more strings that failed to conduct.
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公开(公告)号：US20230395167A1
公开(公告)日：2023-12-07
申请号：US18179505
申请日：2023-03-07
Applicant: Kioxia Corporation
Inventor： Takumi FUJIMORI , Tetsuya SUNATA , Masanobu SHIRAKAWA , Hidehiro SHIGA
CPC classification number: G11C16/3445 , G11C16/16
Abstract: According to an embodiment, a memory system includes: a nonvolatile memory including a plurality of blocks; and a memory controller. The memory controller is configured to: make a comparison between a first erase voltage application accumulated time period and a first erase verify permission time period each corresponding to a first block targeted for erasure; cause the nonvolatile memory to execute a erase voltage application operation in a case where the first erase voltage application accumulated time period is less than the first erase verify permission time period; and cause the nonvolatile memory to execute a erase verify operation in a case where the first erase voltage application accumulated time period is equal to or greater than the first erase verify permission time period.
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公开(公告)号：US11837297B2
公开(公告)日：2023-12-05
申请号：US17344135
申请日：2021-06-10
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang
CPC classification number: G11C16/3495 , G11C16/16 , G11C16/26 , G11C16/3404 , G11C16/3445
Abstract: A method for dynamically adjusting an erase voltage level to be applied in a subsequent erase cycle, comprising: in a current erase cycle, initiating a current erase/verify loop by applying an initial stored erase voltage level according to an erase sequence in which each successive erase/verify loop is incremented by a pre-determined voltage amount, storing an erase/verify loop count, and determining whether the current erase cycle is complete according to a pass criterion. If the erase cycle is complete, a determination is made as to whether the stored erase/verify loop count equals a pre-defined threshold count. Further, if the stored count does not equal the pre-defined threshold count, the initial stored erase voltage level is adjusted such that, upon applying the adjusted erase voltage level in a subsequent erase cycle, an erase/verify loop count will now equal the pre-defined threshold count.
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