公开(公告)号：US09921911B2

公开(公告)日：2018-03-20

申请号：US14787208

申请日：2013-07-31

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Siamak Tavallaei ,  Matthew Schumacher ,  Harvey White, Jr. ,  Chanh Hua

IPC: G11C29/00 ,  G06F11/10 ,  G06F3/06 ,  G11C29/04

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0683 ,  G06F11/1048 ,  G11C2029/0411

Abstract: A system includes off-memory-module ECC-supplemental memory. In a process, an ECC-capable memory controller converts non-ECC data words to ECC data words and distributes each ECC data word between a non-ECC memory module set (of one or more non-ECC memory modules) and the ECC-supplemental memory. A host computer system can include a baseboard on which are mounted an ECC-capable memory controller, off-memory-module ECC-supplemental memory, and sockets for installing non-ECC memory modules.

公开(公告)号：US09904492B2

公开(公告)日：2018-02-27

申请号：US15065915

申请日：2016-03-10

Applicant: Chang-Kyu Seol ,  Jun-Jin Kong ,  Hye-Jeong So ,  Hong-Rak Son ,  Young-Geon Yoo ,  Dong-Whan Lee ,  Dong-Sup Jin

Inventor： Chang-Kyu Seol ,  Jun-Jin Kong ,  Hye-Jeong So ,  Hong-Rak Son ,  Young-Geon Yoo ,  Dong-Whan Lee ,  Dong-Sup Jin

IPC: G06F3/06 ,  G06F11/10 ,  G11C11/56 ,  G11C29/04

CPC classification number: G06F3/0679 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2029/0411

Abstract: Provided are methods for operating a non-volatile memory controller. A method for operating a non-volatile memory controller includes dividing data provided from a host into first unit data and second unit data, encoding the first unit data into first codewords including n number of bits (n is an integer equal to or more than 1), encoding the second unit data into second codewords including n-w number of bits (w is an integer less than n and equal to or more than 1) corresponding to a bit having a value of 0 among the n number of bits of the first codewords, performing bit-to-state mapping on the first codewords and the second codewords using a predetermined bitmap, and programming the first codewords and the second codewords to a first page and a second page of a non-volatile memory, respectively.

公开(公告)号：US20180053545A1

公开(公告)日：2018-02-22

申请号：US15594891

申请日：2017-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil SON

IPC: G11C11/419 ,  G06F11/10 ,  G11C7/18 ,  G11C29/04 ,  G11C7/08

CPC classification number: G11C11/419 ,  G06F11/1048 ,  G11C7/08 ,  G11C7/18 ,  G11C29/04 ,  G11C29/42 ,  G11C2029/0411

Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, an internal processing circuit, and an error correction circuit. The control logic circuit generates an internal processing mode signal in response to a command from a memory controller. The internal processing circuit selectively performs the internal processing operation on a first set of data read from the memory cell array to output a processing result data, in response to the internal processing mode signal. The error correction circuit performs an error correction code (ECC) encoding on the processing result data to generate a second parity data and stores the processing result data and the second parity data in the memory cell array. The error correction circuit generates the second parity data by selecting the same ECC of a plurality of ECCs as a first ECC.

公开(公告)号：US09899104B2

公开(公告)日：2018-02-20

申请号：US15073665

申请日：2016-03-18

Applicant: Silicon Motion Inc.

Inventor： Yu-Luen Wang

IPC: H03M13/00 ,  G11C29/42 ,  G11C29/44 ,  H03M13/15 ,  H03M13/29

CPC classification number: G11C29/42 ,  G11C29/44 ,  G11C2029/0411 ,  H03M13/1515 ,  H03M13/2906

Abstract: A RAID decoding system for performing a Built in Self-Test (BIST) includes: an Error Insertion block for inserting errors into a first Reed-Solomon (RS) codeword and a second RS codeword; and a RAID decoder. The RAID decoder includes: a storage, for storing a syndrome of the first codeword, a syndrome of the second codeword, parity data of the first RS codeword and parity data of the second RS codeword; and a first RS decoder and a second RS decoder for storing the first RS codeword and the second RS codeword, respectively, and for performing decoding on the first RS codeword and the second RS codeword according to the parity data to generate an updated syndrome of the first RS codeword and an updated syndrome of the second RS codeword.

公开(公告)号：US20180048434A1

公开(公告)日：2018-02-15

申请号：US15674134

申请日：2017-08-10

Applicant: SK Hynix Memory Solutions Inc.

Inventor： Naveen KUMAR ,  Aman BHATIA ,  Yi-Min LIN

IPC: H04L1/20 ,  G11C29/50 ,  G11C16/34 ,  G06F11/07

CPC classification number: H04L1/203 ,  G06F11/076 ,  G06F11/1012 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50004 ,  G11C29/52 ,  G11C29/56008 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/5004

Abstract: An apparatus of a memory system and an operating method thereof includes: a plurality of memory devices; and a controller including a decoder and a BER predictor, coupled with the plurality of memory devices, configured to perform a decoding iteration includes to conduct NAND read and generate NAND data; decode in accordance with the NAND data and generate decoder information by the decoder; predict a BER in accordance with at least the decode information by the BER predictor; and evaluate the predicted BER and generate evaluation result by the BER predictor.

公开(公告)号：US09880899B2

公开(公告)日：2018-01-30

申请号：US14712756

申请日：2015-05-14

Applicant: Pure Storage, Inc.

Inventor： John D. Davis ,  John Hayes ,  Zhangxi Tan ,  Hari Kannan ,  Nenad Miladinovic

IPC: G06F11/10 ,  G06F17/30 ,  G11C16/34 ,  G11C29/52 ,  G06F11/07 ,  G11C29/44 ,  G06F12/02 ,  G11C29/04

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/1048 ,  G06F12/0246 ,  G06F17/30194 ,  G06F17/302 ,  G06F2212/7207 ,  G06F2212/7208 ,  G06F2212/7211 ,  G11C16/349 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: In some embodiments, a method for die-level monitoring is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes. Each of the storage nodes has a non-volatile solid-state storage with non-volatile memory and the user data is accessible via the erasure coding from a remainder of the storage nodes in event of two of the storage nodes being unreachable. The method includes producing diagnostic information that diagnoses the non-volatile memory on a basis of per package, per die, per plane, per block, or per page, the producing performed by each of the plurality of storage nodes. The method includes writing the diagnostic information to a memory in the storage cluster.

公开(公告)号：US20180025777A1

公开(公告)日：2018-01-25

申请号：US15213581

申请日：2016-07-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： ADAM JACOBVITZ ,  XINDE HU

IPC: G11C11/56 ,  G11C29/52 ,  G06F3/06 ,  G06F11/10

CPC classification number: G11C29/52 ,  G06F11/1072 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/349 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2211/563 ,  G11C2211/5644

Abstract: A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is configured, based on a metric associated with a portion of the non-volatile memory, to store a read technique indicator that indicates that the portion is to be read using a high-reliability read technique.

公开(公告)号：US20180018171A1

公开(公告)日：2018-01-18

申请号：US15717762

申请日：2017-09-27

Applicant: Xitore, Inc.

Inventor： Mike Hossein Amidi ,  Fariborz Frankie Roohparvar

IPC: G06F9/30 ,  G06F3/06 ,  G06F12/10 ,  G06F12/02 ,  G06F11/10 ,  G11C29/52 ,  G06F12/06 ,  G11C29/04 ,  G11C8/06

CPC classification number: G06F9/30 ,  G06F3/0605 ,  G06F3/0619 ,  G06F3/0635 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0673 ,  G06F3/0679 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1068 ,  G06F12/0223 ,  G06F12/0246 ,  G06F12/06 ,  G06F12/0638 ,  G06F12/0802 ,  G06F12/0888 ,  G06F12/10 ,  G06F13/00 ,  G06F2206/1014 ,  G06F2212/152 ,  G06F2212/205 ,  G06F2212/261 ,  G06F2212/401 ,  G06F2212/403 ,  G11C8/06 ,  G11C29/52 ,  G11C2029/0411

Abstract: A hybrid memory system provides rapid, persistent byte-addressable and block-addressable memory access to a host computer system by providing direct access to a both a volatile byte-addressable memory and a volatile block-addressable memory via the same parallel memory interface. The hybrid memory system also has at least a non-volatile block-addressable memory that allows the system to persist data even through a power-loss state. The hybrid memory system can copy and move data between any of the memories using local memory controllers to free up host system resources for other tasks.

公开(公告)号：US20180013451A1

公开(公告)日：2018-01-11

申请号：US15206799

申请日：2016-07-11

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. Kaynak ,  Patrick R. Khayat ,  Sivagnanam Parthasarathy ,  Nicholas J. Richardson

IPC: H03M13/45 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11

CPC classification number: H03M13/116 ,  G06F11/1068 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  H03M13/1128 ,  H03M13/114 ,  H03M13/152 ,  H03M13/2906 ,  H03M13/2927 ,  H03M13/3753

Abstract: One example of layer-by-layer error correction can include iteratively error correcting the codeword on a layer-by-layer basis with the first error correction circuit in a first mode and determining on the layer-by-layer basis whether a number of parity errors in a particular layer is less than a threshold number of parity errors. The codeword can be transferred to a second error correction circuit when the number of parity errors is less than the threshold number of parity errors. The codeword can be iteratively error corrected with the first error correction circuit in a second mode when the number of parity errors is at least the threshold number of parity errors. The threshold number of parity errors can be at least partially based on an adjustable code rate of the first error correction circuit or the second error correction circuit.

公开(公告)号：US20180011753A1

公开(公告)日：2018-01-11

申请号：US15639019

申请日：2017-06-30

Applicant: Seagate Technology LLC

Inventor： AbdelHakim S. Alhussien ,  Sundararajan Sankaranarayanan ,  Erich F. Haratsch

IPC: G06F11/07 ,  G11C16/08 ,  G11C11/56 ,  G11C16/26

CPC classification number: G06F11/076 ,  G06F11/0727 ,  G06F11/0775 ,  G06F11/1012 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/26 ,  G11C16/28 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/3707 ,  H03M13/3723 ,  H03M13/612 ,  H03M13/6325

Abstract: Adaptive read threshold voltage tracking techniques are provided that employ bit error rate estimation based on a non-linear syndrome weight mapping. An exemplary device comprises a controller configured to determine a bit error rate for at least one of a plurality of read threshold voltages in a memory using a non-linear mapping of a syndrome weight to the bit error rate for the at least one of the plurality of read threshold voltages.