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    Information processing method and device and computer storage medium
    1.
    发明授权
    Information processing method and device and computer storage medium 有权

    公开(公告)号：US11811422B2

    公开(公告)日：2023-11-07

    申请号：US17413089

    申请日：2019-12-12

    Applicant: SANECHIPS TECHNOLOGY CO., LTD.

    Inventor： Huayong Wang

    IPC: H03M13/11

    CPC classification number: H03M13/1168 ,  H03M13/114 ,  H03M13/1108 ,  H03M13/1137

    Abstract: Provided is an information processing method. The method includes that: first data to be decoded and one or more decoding parameters of the first data are obtained; a basis matrix is determined based on the one or more decoding parameters; a decoding instruction set including a plurality of decoding instructions is determined based on the basis matrix, wherein the plurality of decoding instructions include elements in the basis matrix; and the first data is decoded based on the decoding instruction set. Further provided are an information processing device and a computer storage medium.

    METHOD AND APPARATUS OF A FULLY-PIPELINED LAYERED LDPC DECODER
    2.
    发明申请
    METHOD AND APPARATUS OF A FULLY-PIPELINED LAYERED LDPC DECODER 审中-公开

    公开(公告)号：US20190222227A1

    公开(公告)日：2019-07-18

    申请号：US16277890

    申请日：2019-02-15

    Applicant: TensorCom, Inc.

    Inventor： Bo Xia ,  Ricky Lap Kei Cheung ,  Bo Lu

    IPC: H03M13/11

    CPC classification number: H03M13/1145 ,  H03M13/1122 ,  H03M13/114 ,  H03M13/1148 ,  H03M13/116

    Abstract: Processors are arranged in a pipeline structure to operate on multiple layers of data, each layer comprising multiple groups of data. An input to a memory is coupled to an output of the last processor in the pipeline, and the memory's output is coupled to an input of the first processor in the pipeline. Multiplexing and de-multiplexing operations are performed in the pipeline. For each group in each layer, a stored result read from the memory is applied to the first processor in the pipeline structure. A calculated result of the stored result is output at the last processor and stored in the memory. Once processing for the last group of data in a first layer is completed, the corresponding processor is configured to process data in a next layer before the pipeline finishes processing the first layer. The stored result obtained from the next layer comprises a calculated result produced from a layer previous to the first layer.

    LDPC PERFORMANCE IMPROVEMENT USING SBE-LBD DECODING METHOD AND LBD COLLISION REDUCTION
    5.
    发明申请
    LDPC PERFORMANCE IMPROVEMENT USING SBE-LBD DECODING METHOD AND LBD COLLISION REDUCTION 审中-公开

    公开(公告)号：US20180048328A1

    公开(公告)日：2018-02-15

    申请号：US15237341

    申请日：2016-08-15

    Applicant: Hughes Network Systems, LLC

    Inventor： Gaurav Bhatia ,  Qiujun Huang ,  Mustafa Eroz

    IPC: H03M13/11 ,  H04L1/00

    CPC classification number: H03M13/1105 ,  H03M13/1111 ,  H03M13/114 ,  H03M13/6566 ,  H04L1/0045 ,  H04L1/0058

    Abstract: Systems and methods are described for performing Layered Belief LDPC decoding on received Standard Belief LDPC encoded data bursts. In on implementation, a receiver: demodulates a signal, the demodulated signal including a noise corrupted signal derived from a codeword encoded using standard belief LDPC encoding; converts the noise corrupted signal derived from the standard belief LDPC encoded codeword to a noise corrupted signal derived from a layered belief LDPC encoded codeword; and decodes the noise corrupted signal derived from the layered belief LDPC encoded codeword using a layered belief LDPC decoder. In further implementations, systems are described for reducing collisions in Layered Belief LDPC decoders that occur when multiple parity checks need the same soft decision at the same time. In these implementations, elements in an original LBD decoder table are rearranged to increase the distance between elements specifying the same location in a RAM where soft decisions are stored.

    METHOD AND SYSTEM FOR LDPC DECODING
    6.
    发明申请
    METHOD AND SYSTEM FOR LDPC DECODING 审中-公开

    公开(公告)号：US20180013446A1

    公开(公告)日：2018-01-11

    申请号：US15619764

    申请日：2017-06-12

    Applicant: Maxlinear, Inc.

    Inventor： Mario Milicevic ,  Glenn Gulak

    IPC: H03M13/11 ,  H03M13/37

    CPC classification number: H03M13/1174 ,  H03M13/112 ,  H03M13/1122 ,  H03M13/1128 ,  H03M13/114 ,  H03M13/116 ,  H03M13/3746 ,  H03M13/635 ,  H03M13/6502 ,  H03M13/6505 ,  H03M13/6516

    Abstract: A Low-Density Parity-Check (LDPC) decoder and a method for LDPC decoding are provided. The LDPC decoder receives a soft-decision input codeword block in which the probability of a bit being a “0” or a “1” is represented as a log-likelihood ratio (LLR). During LDPC decoding, a sequence of hardware logic units iteratively updates the soft-decision input codeword block until a valid codeword is found or a maximum number of decoding iterations is reached. Each hardware logic unit comprises a check node (CN) update logic unit and a variable node (VN) update logic unit. The CN update logic units are coupled via a closed CN path, and the VN update logic units are coupled via a closed VN path. Aspects of this LDPC decoder alleviate the global routing and energy efficiency challenges of traditional LDPC decoders, to enable multi-rate, multi-Gb/s decoding without compromising error correction performance in next-generation systems and future CMOS technology nodes.

    Method and device for forward error correction decoder system utilizing orthogonality of an H matrix
    7.
    发明授权
    Method and device for forward error correction decoder system utilizing orthogonality of an H matrix 有权

    公开(公告)号：US09742439B1

    公开(公告)日：2017-08-22

    申请号：US14733288

    申请日：2015-06-08

    Applicant: Microsemi Solutions (U.S.), Inc.

    Inventor： Peter Graumann

    IPC: H03M13/00 ,  H03M13/05 ,  H03M13/11

    CPC classification number: H03M13/1111 ,  H03M13/114 ,  H03M13/116 ,  H03M13/616

    Abstract: A method and apparatus for a quasi-cyclic low density parity check (QC-LDPC) decoder utilizes a parity check matrix (H matrix) having a matrix value for each row and column position in the matrix. Each matrix value is associated with an initial soft information element where, for each one of the matrix values associated with a constrained row, the one of the matrix values is constrained to a set of constraint values associated with a set of initial soft information elements. The set of initial soft information elements excludes a number of soft information elements that immediately precede a first initial soft information element. The first initial soft information element is associated with a selected first matrix value associated with a first row that immediately precedes the constrained row, and with the same column as the one of the matrix values in the constrained row.

    Systems and methods for processing LDPC codes with different circulant sizes
    9.
    发明授权
    Systems and methods for processing LDPC codes with different circulant sizes 有权
    用于处理不同循环尺寸的LDPC码的系统和方法

    公开(公告)号：US09548759B1

    公开(公告)日：2017-01-17

    申请号：US14554845

    申请日：2014-11-26

    Applicant: Marvell International Ltd.

    Inventor： Farshid Rafiee Rad

    IPC: H03M13/11 ,  H03M13/37

    CPC classification number: H03M13/116 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/6516

    Abstract: Systems and methods are provided for decoding low density parity check (LDPC) codes with different circulant sizes using common decoding circuitry. The systems and methods include receiving a plurality of codewords corresponding to an LDPC code and determining a circulant size associated with the plurality of received codewords. In response to determining the circulant size associated with the plurality of received codewords, the systems and methods partition processing resources of the common decoding circuitry into a plurality of cells based on the determined circulant size and processing the plurality of received codewords simultaneously using the plurality of cells.

    Abstract translation: 提供了用于使用公共解码电路解码具有不同循环尺寸的低密度奇偶校验（LDPC）码的系统和方法。 系统和方法包括接收对应于LDPC码的多个码字，并确定与多个接收码字相关联的循环大小。 响应于确定与多个接收码字相关联的循环大小，系统和方法基于确定的循环大小将公共解码电路的处理资源划分为多个小区，并且使用多个接收码字同时处理多个接收码字 细胞。

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