公开(公告)号：US09627046B2

公开(公告)日：2017-04-18

申请号：US14635918

申请日：2015-03-02

Applicant: SanDisk Technologies LLC

Inventor： Kenneth Louie ,  Man Mui

IPC: G11C16/06 ,  G11C11/56 ,  G11C16/34 ,  G11C7/14 ,  G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  G11C16/32

CPC classification number: G11C11/5628 ,  G11C7/14 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459

Abstract: Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a word lines, different data states are written individually, while programming inhibiting the other states, thereby breaking down the write operation into a number of sub-operations, one for each state to be written. This allows for improved timing and decreased power consumption.

公开(公告)号：US20170103816A1

公开(公告)日：2017-04-13

申请号：US15384714

申请日：2016-12-20

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Shinya OKUNO ,  Shigeki NAGASAKA ,  Toshiyuki KOUCHI

IPC: G11C16/32 ,  G06F13/16 ,  G06F5/06 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/32 ,  G06F5/06 ,  G06F13/1673 ,  G06F2205/067 ,  G11C7/02 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1066 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C2207/108 ,  G11C2207/2281 ,  Y02D10/14

Abstract: According to one embodiment, a semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

公开(公告)号：US09620653B2

公开(公告)日：2017-04-11

申请号：US14971743

申请日：2015-12-16

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Masao Shingu ,  Jun Fujiki ,  Naoki Yasuda ,  Koichi Muraoka

IPC: H01L29/51 ,  H01L29/788 ,  H01L21/28 ,  H01L29/792 ,  G11C11/40 ,  G11C16/04 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/423 ,  H01L29/49 ,  G11C16/10 ,  H01L27/11521

CPC classification number: H01L29/7883 ,  G11C11/40 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/788 ,  H01L29/792

Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.

公开(公告)号：US09620221B1

公开(公告)日：2017-04-11

申请号：US15140710

申请日：2016-04-28

Applicant: SK hynix Inc.

Inventor： Myeong Cheol Son

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/12

Abstract: There may be provided a semiconductor memory device and an operating method thereof. A semiconductor memory device may include a memory cell array including a plurality of memory strings. The semiconductor memory device may include a peripheral circuit for performing a program operation on the plurality of memory strings, and a control logic for controlling the peripheral circuit to perform the program operation. The control logic may control the peripheral circuit to adjust potential levels of program permission voltages to be applied to the plurality of memory strings according to arrangement positions of the memory strings.

公开(公告)号：US09589661B2

公开(公告)日：2017-03-07

申请号：US14556107

申请日：2014-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Ryun Kim

IPC: G11C16/34 ,  G11C11/56 ,  G06F11/07 ,  G06F11/10 ,  G11C16/12 ,  G11C29/02 ,  G11C29/42 ,  G11C29/52 ,  H03M13/05 ,  H03M13/09 ,  H03M13/19

CPC classification number: G11C16/3495 ,  G06F11/076 ,  G06F11/10 ,  G06F11/1048 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/12 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C29/52 ,  H03M13/05 ,  H03M13/09 ,  H03M13/19

Abstract: A method of programming target memory cells of a nonvolatile memory device includes; programming the target memory cells using an incrementally adjusted program time, reading a code word stored by the target memory cells and determining a bit error rate (BER) associated with the target memory cells in view of the read code word, and if the BER exceeds an upper BER limit, increasing the program time by a unit time.

Abstract translation: 一种编程非易失存储器件的目标存储单元的方法包括： 使用增量调整的编程时间来编程目标存储器单元，读取由目标存储器单元存储的代码字，并且鉴于读取的代码字确定与目标存储器单元相关联的误码率（BER），并且如果BER超过 BER上限，将程序时间增加一个单位时间。

公开(公告)号：US20170053702A1

公开(公告)日：2017-02-23

申请号：US15219903

申请日：2016-07-26

Applicant: SK hynix Inc.

Inventor： Herve' Caracciolo

IPC: G11C16/12 ,  G11C16/30

CPC classification number: G11C16/12 ,  G05F1/575 ,  G11C7/14 ,  G11C16/30

Abstract: Disclosed herein is a regulator for a non-volatile memory is provided. The regulator comprises an operational amplifier for receiving a reference voltage and a feedback voltage to output a voltage amplifying the difference of the reference voltage and the feedback voltage, the feedback voltage being obtained by dividing an output voltage of the regulator; a first switching unit turning on in response to the amplified voltage; a second switching unit electrically connected between a first node and the first switching unit for protecting the first switching unit from the voltage of the first node; and a third switching unit providing the output voltage of the regulator to a second node in response to a voltage of the first node.

Abstract translation: 本文公开了一种用于非易失性存储器的调节器。 调节器包括用于接收参考电压和反馈电压的运算放大器，以输出放大参考电压和反馈电压的差的电压，反馈电压通过分压调节器的输出电压而获得; 第一开关单元响应于放大的电压而导通; 电连接在第一节点和第一开关单元之间的第二开关单元，用于保护第一开关单元免于第一节点的电压; 以及第三开关单元，其响应于所述第一节点的电压将所述调节器的输出电压提供给第二节点。

公开(公告)号：US09576675B2

公开(公告)日：2017-02-21

申请号：US14969351

申请日：2015-12-15

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Jin-Ki Kim ,  Peter B. Gillingham

IPC: G11C16/06 ,  G11C16/30 ,  G11C5/14 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C5/143 ,  G11C5/145 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

Abstract translation: 存储器件包括诸如用于存储数据的闪存的核心存储器。 存储器件包括用于接收用于为闪速存储器供电的第一电压的第一电源输入。 另外，存储器件包括用于接收第二电压的第二电源输入。 存储器件包括被配置为接收第二电压并导出一个或多个内部电压的电源管理电路。 电源管理电路将内部电压提供或传送到闪存。 由功率管理电路（例如，电压转换器电路）产生并提供给核心存储器的不同的内部电压使得诸如针对核心存储器中的单元的读取/编程/擦除的操作。

公开(公告)号：US09558840B2

公开(公告)日：2017-01-31

申请号：US14844174

申请日：2015-09-03

Applicant: Kabushiki Kaisha Toshiba

Inventor： Shinya Okuno ,  Shigeki Nagasaka ,  Toshiyuki Kouchi

IPC: G11C7/00 ,  G11C16/32 ,  G11C16/10 ,  G11C16/26 ,  G11C16/16 ,  G11C16/12 ,  G11C16/04

CPC classification number: G11C16/32 ,  G06F5/06 ,  G06F13/1673 ,  G06F2205/067 ,  G11C7/02 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1066 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C2207/108 ,  G11C2207/2281 ,  Y02D10/14

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed closer to the input/output circuit than the first FIFO.

Abstract translation: 半导体器件包括存储器电路，第一FIFO，第二FIFO和输入/输出电路。 存储电路输出数据。 第一FIFO从存储器电路接收数据并与第一时钟信号同步地输出数据。 第二个FIFO接收从第一个FIFO输出的数据，并与第一个时钟信号同步输出数据。 输入/输出电路输出从第二个FIFO输出的数据。 第二个FIFO比第一个FIFO更靠近输入/输出电路。

公开(公告)号：US09552883B1

公开(公告)日：2017-01-24

申请号：US14990230

申请日：2016-01-07

Applicant: SK hynix Inc.

Inventor： Sung Wook Jung

IPC: G11C11/34 ,  G11C16/12 ,  G11C16/34

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/3459 ,  G11C2211/5621

Abstract: A semiconductor memory device includes a plurality of memory cells connected to a plurality of word lines; a peripheral circuit suitable for applying a program pulse to at least one of the word lines, performing a program verification operation to the plurality of memory cells by using a first program verification voltage; and a control logic suitable for controlling the peripheral circuit to repeat the applying of the program pulse and the performing the program verification operation until program verification passes by increasing a level of the program pulse by an amount of a step voltage at each repetition, wherein a size of the step voltage decreases at each repetition.

Abstract translation: 半导体存储器件包括连接到多个字线的多个存储单元; 适用于向至少一个字线施加编程脉冲的外围电路，通过使用第一程序验证电压对所述多个存储单元执行程序验证操作; 以及适于控制外围电路重复施加编程脉冲并执行程序验证操作的控制逻辑，直到程序验证通过，通过将编程脉冲的电平增加每次重复的步进电压的量，其中a 每次重复时阶梯电压的大小都会降低。

公开(公告)号：US20170010836A1

公开(公告)日：2017-01-12

申请号：US15207414

申请日：2016-07-11

Applicant: HGST Technologies Santa Ana, Inc.

Inventor： Ashot MELIK-MARTIROSIAN

IPC: G06F3/06 ,  G06F11/07 ,  G11C16/14 ,  G11C16/12 ,  G11C16/34

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0679 ,  G06F11/0727 ,  G06F11/076 ,  G06F11/079 ,  G11C16/12 ,  G11C16/14 ,  G11C16/349 ,  G11C16/3495

Abstract: A method populates a parameter set for dynamically adjusting an operating condition in a memory block of a non-volatile memory circuit. A desired condition limit is identified, and a first parameter is computed as a function of a first memory operation to be performed on the memory block. The first parameter is included in a parameter set, and the memory block is cycled until the operating condition reaches the desired condition limit. After cycling, a second parameter is determined as a function of a second memory operation to be performed on the memory block, and the second parameter is included in the parameter set. The steps of cycling, and determining and the including the second parameter may be repeated until a desired number of cycles/parameters are reached. A retention bake may also be performed on the memory circuit, and a bit error rate resulting from a read operation verified.

Abstract translation: 方法填充用于动态调整非易失性存储器电路的存储器块中的操作条件的参数集。 识别期望的条件限制，并且根据要对存储器块执行的第一存储器操作来计算第一参数。 第一个参数包含在一个参数组中，循环使用内存块，直到操作条件达到所需条件限制为止。 在循环之后，根据对存储器块执行的第二存储器操作来确定第二参数，并且第二参数被包括在参数组中。 可以重复循环，确定和包括第二参数的步骤，直到达到所需数量的循环/参数。 还可以在存储器电路上执行保留烘烤，并且验证由读取操作产生的误码率。