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    Multiple register clock driver loaded memory subsystem
    52.
    发明授权
    Multiple register clock driver loaded memory subsystem 有权

    公开(公告)号：US11797229B2

    公开(公告)日：2023-10-24

    申请号：US17360943

    申请日：2021-06-28

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

    IPC: G06F3/06 ,  G06F1/04 ,  G06F13/16

    CPC classification number: G06F3/0659 ,  G06F1/04 ,  G06F13/1689 ,  G06F2213/16

    Abstract: A memory subsystem architecture that includes two register clock driver (RCD) devices to increase a number of output drivers for signaling memories of the memory subsystem is described herein. In a two RCD device implementation, first and second RCD devices may contemporaneously provide first subchannel C/A information and second subchannel C/A information, respectively, to respective first and second group of memories of the memory subsystem responsive to a common clock signal. Because each of the first and second RCD devices operate responsive to the common clock signal, operation of the first and second RCD devices may be synchronized such that all subchannel driver circuits drive respective subchannel C/A information contemporaneously.

    Memory system, memory controller and memory chip
    56.
    发明授权
    Memory system, memory controller and memory chip 有权

    公开(公告)号：US11789893B2

    公开(公告)日：2023-10-17

    申请号：US17391755

    申请日：2021-08-02

    Applicant: ETRON TECHNOLOGY, INC.

    Inventor： Chun Shiah

    IPC: G06F13/42 ,  G06F13/16

    CPC classification number: G06F13/4291 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/423

    Abstract: A memory system comprises a memory and a physical layer circuit. The memory system comprises a memory, a data bus and a single-pin STB. The memory receives a parallel command though the data bus, and receives a serial command through the STB. The physical layer circuit is configured to transmit the parallel command to the data bus. The physical layer circuit is configured to convert STB input data from the controller into the serial command and transmit the serial command to the STB.

    Deterministic operation of storage class memory
    58.
    发明授权
    Deterministic operation of storage class memory 有权

    公开(公告)号：US11755509B2

    公开(公告)日：2023-09-12

    申请号：US17715404

    申请日：2022-04-07

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent Haukness

    IPC: G06F13/16

    CPC classification number: G06F13/1689

    Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory controller is disclosed. The memory controller includes write queue logic that has first storage to temporarily store signal components of a write operation. The signal components include an address and write data. A transfer interface issues the signal components of the write operation to a bank of a storage class memory (SCM) device and generates a time value. The time value represents a minimum time interval after which a subsequent write operation can be issued to the bank. The write queue logic includes an issue queue to store the address and the time value for a duration corresponding to the time value.

    HIGH CAPACITY, HIGH PERFORMANCE MEMORY SYSTEM
    60.
    发明公开
    HIGH CAPACITY, HIGH PERFORMANCE MEMORY SYSTEM 审中-公开

    公开(公告)号：US20230266923A1

    公开(公告)日：2023-08-24

    申请号：US18121231

    申请日：2023-03-14

    Applicant: Rambus Inc.

    Inventor： Frederick WARE

    IPC: G06F3/06 ,  G06F12/06 ,  G06F13/40 ,  G06F13/16 ,  G06F13/42

    CPC classification number: G06F3/0659 ,  G06F12/06 ,  G06F13/4086 ,  G06F13/1689 ,  G06F13/4256 ,  G06F13/1684

    Abstract: Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.

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