公开(公告)号：US20230289190A1

公开(公告)日：2023-09-14

申请号：US17691288

申请日：2022-03-10

申请人： NVIDIA Corporation

发明人： Apoorv PARLE ,  Ronny KRASHINSKY ,  John EDMONDSON ,  Jack CHOQUETTE ,  Shirish GADRE ,  Steve HEINRICH ,  Manan PATEL ,  Prakash Bangalore PRABHAKAR, JR. ,  Ravi MANYAM ,  Wish GANDHI ,  Lacky SHAH ,  Alexander L. Minkin

IPC分类号： G06F9/38 ,  G06F9/52 ,  G06F13/40 ,  G06F13/16 ,  H04L49/101 ,  G06T1/20 ,  G06T1/60

CPC分类号： G06F9/3887 ,  G06F9/522 ,  G06F13/4022 ,  G06F13/1689 ,  H04L49/101 ,  G06T1/20 ,  G06T1/60

摘要： This specification describes a programmatic multicast technique enabling one thread (for example, in a cooperative group array (CGA) on a GPU) to request data on behalf of one or more other threads (for example, executing on respective processor cores of the GPU). The multicast is supported by tracking circuitry that interfaces between multicast requests received from processor cores and the available memory. The multicast is designed to reduce cache (for example, layer 2 cache) bandwidth utilization enabling strong scaling and smaller tile sizes.

公开(公告)号：US20230289215A1

公开(公告)日：2023-09-14

申请号：US17691621

申请日：2022-03-10

申请人： NVIDIA Corporation

发明人： Greg PALMER ,  Gentaro HIROTA ,  Ronny KRASHINSKY ,  Ze LONG ,  Brian PHARRIS ,  Rajballav DASH ,  Jeff TUCKEY ,  Jerome F. DULUK, JR. ,  Lacky SHAH ,  Luke DURANT ,  Jack CHOQUETTE ,  Eric WERNESS ,  Naman GOVIL ,  Manan PATEL ,  Shayani DEB ,  Sandeep NAVADA ,  John EDMONDSON ,  Prakash BANGALORE PRABHAKAR ,  Wish GANDHI ,  Ravi MANYAM ,  Apoorv PARLE ,  Olivier GIROUX ,  Shirish GADRE ,  Steve HEINRICH

IPC分类号： G06F9/48 ,  G06F9/38 ,  G06F9/30 ,  G06F9/54

CPC分类号： G06F9/4881 ,  G06F9/3851 ,  G06F9/3009 ,  G06F9/544

摘要： A new level(s) of hierarchy—Cooperate Group Arrays (CGAs)—and an associated new hardware-based work distribution/execution model is described. A CGA is a grid of thread blocks (also referred to as cooperative thread arrays (CTAs)). CGAs provide co-scheduling, e.g., control over where CTAs are placed/executed in a processor (such as a GPU), relative to the memory required by an application and relative to each other. Hardware support for such CGAs guarantees concurrency and enables applications to see more data locality, reduced latency, and better synchronization between all the threads in tightly cooperating collections of CTAs programmably distributed across different (e.g., hierarchical) hardware domains or partitions.

公开(公告)号：US20240289132A1

公开(公告)日：2024-08-29

申请号：US18660763

申请日：2024-05-10

申请人： NVIDIA Corporation

发明人： Apoorv PARLE ,  Ronny KRASHINSKY ,  John EDMONDSON ,  Jack CHOQUETTE ,  Shirish GADRE ,  Steve HEINRICH ,  Manan PATEL ,  Prakash Bangalore PRABHAKAR, JR. ,  Ravi MANYAM ,  Wish GANDHI ,  Lacky SHAH ,  Alexander L. Minkin

IPC分类号： G06F9/38 ,  G06F9/52 ,  G06F13/16 ,  G06F13/40 ,  G06T1/20 ,  G06T1/60 ,  H04L49/101

CPC分类号： G06F9/3887 ,  G06F9/522 ,  G06F13/1689 ,  G06F13/4022 ,  G06T1/20 ,  G06T1/60 ,  H04L49/101

摘要： This specification describes a programmatic multicast technique enabling one thread (for example, in a cooperative group array (CGA) on a GPU) to request data on behalf of one or more other threads (for example, executing on respective processor cores of the GPU). The multicast is supported by tracking circuitry that interfaces between multicast requests received from processor cores and the available memory. The multicast is designed to reduce cache (for example, layer 2 cache) bandwidth utilization enabling strong scaling and smaller tile sizes.

公开(公告)号：US20230289189A1

公开(公告)日：2023-09-14

申请号：US17691690

申请日：2022-03-10

申请人： NVIDIA Corporation

发明人： Prakash BANGALORE PRABHAKAR ,  Gentaro HIROTA ,  Ronny KRASHINSKY ,  Ze LONG ,  Brian PHARRIS ,  Rajballav DASH ,  Jeff TUCKEY ,  Jerome F. DULUK, JR. ,  Lacky SHAH ,  Luke DURANT ,  Jack CHOQUETTE ,  Eric WERNESS ,  Naman GOVIL ,  Manan PATEL ,  Shayani DEB ,  Sandeep NAVADA ,  John EDMONDSON ,  Greg PALMER ,  Wish GANDHI ,  Ravi MANYAM ,  Apoorv PARLE ,  Olivier GIROUX ,  Shirish GADRE ,  Steve HEINRICH

IPC分类号： G06F3/06

CPC分类号： G06F3/064 ,  G06F3/0604 ,  G06F3/0679

摘要： Distributed shared memory (DSMEM) comprises blocks of memory that are distributed or scattered across a processor (such as a GPU). Threads executing on a processing core local to one memory block are able to access a memory block local to a different processing core. In one embodiment, shared access to these DSMEM allocations distributed across a collection of processing cores is implemented by communications between the processing cores. Such distributed shared memory provides very low latency memory access for processing cores located in proximity to the memory blocks, and also provides a way for more distant processing cores to also access the memory blocks in a manner and using interconnects that do not interfere with the processing cores' access to main or global memory such as hacked by an L2 cache. Such distributed shared memory supports cooperative parallelism and strong scaling across multiple processing cores by permitting data sharing and communications previously possible only within the same processing core.