公开(公告)号：US20240071941A1

公开(公告)日：2024-02-29

申请号：US17897648

申请日：2022-08-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Fa Chen ,  Yun-Han Lee ,  Lee-Chung Lu

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/5386 ,  H01L21/486 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0655 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696 ,  H01L23/5385 ,  H01L2224/08225 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/13081

Abstract: A semiconductor device includes: a first chip including a plurality of first device features and a plurality of first interconnect structures disposed above the first device features; a second chip including a plurality of second device features and a plurality of second interconnect structures disposed above the second device features; and an interposer bonded to the first chip and the second chip, and disposed on an opposite side from the first and second device features with respect to the first and second interconnect structures; wherein the interposer includes a plurality of power rails configured to deliver power to the first and second chips.

公开(公告)号：US20230333981A1

公开(公告)日：2023-10-19

申请号：US18341088

申请日：2023-06-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsien-Hsin Sean Lee ,  William Wu Shen ,  Yun-Han Lee

IPC: G06F12/0804 ,  G11C5/04 ,  G11C5/02 ,  G06F12/0891 ,  G11C7/22

CPC classification number: G06F12/0804 ,  G11C5/04 ,  G11C5/025 ,  G06F12/0891 ,  G11C7/22 ,  H01L2224/16225 ,  H01L2924/15311 ,  G06F2212/1008 ,  G06F2212/1032 ,  G06F2212/45 ,  G06F2212/608

Abstract: A memory system includes multiple groups of primary memory cells residing in a first die or a stack of first dies, multiple groups of cache memory cells residing in a second die, an interposer, and control circuits residing in a third die. Each group of the cache memory cells is associated with a corresponding group of the primary memory cells. The first die or the stack of first dies is coupled to a top surface of the second die through a first group of bumps. A bottom surface of the second die is coupled to a top surface of the interposer through a second group of bumps. The control circuits are associated with the primary memory cells and the cache memory cells. The third die is positioned aside the second die and coupled to the top surface of the interposer through a third group of pumps.

公开(公告)号：US11715668B2

公开(公告)日：2023-08-01

申请号：US17371438

申请日：2021-07-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Jr Huang ,  William Wu Shen ,  Chin-Her Chien ,  Chin-Chou Liu ,  Yun-Han Lee

IPC: H01Q1/48 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L23/66 ,  H01Q1/22 ,  H01Q9/04 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L21/76898 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/66 ,  H01Q1/2283 ,  H01Q1/48 ,  H01Q9/0407 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L2223/6677 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2924/1423 ,  H01L2924/157 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2224/131 ,  H01L2924/014

Abstract: The present disclosure relates to a semiconductor module. The semiconductor module includes an excitable element located on a first side of a substrate. A first ground structure is disposed between the first side of the substrate and the excitable element. The first ground structure includes a conductive via extending through the substrate and an interconnect disposed over a topmost surface of the conductive via facing away from the substrate. A second ground structure is located on a second side of the substrate, opposing the first side, and electrically coupled to the first ground structure.

公开(公告)号：US11562946B2

公开(公告)日：2023-01-24

申请号：US17209878

申请日：2021-03-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED

Inventor： Hidehiro Fujiwara ,  Tze-Chiang Huang ,  Hong-Chen Cheng ,  Yen-Huei Chen ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yun-Han Lee ,  Lee-Chung Lu

IPC: G11C11/00 ,  H01L23/48 ,  G11C11/418 ,  H01L21/768 ,  H01L27/11

Abstract: A memory macro structure includes a first memory array, a second memory array, a cell activation circuit coupled to the first and second memory arrays and positioned between the first and second memory arrays, a control circuit coupled to the cell activation circuit and positioned adjacent to the cell activation circuit, and a through-silicon via (TSV) extending through one of the cell activation circuit or the control circuit.

公开(公告)号：US10673603B2

公开(公告)日：2020-06-02

申请号：US14921205

申请日：2015-10-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Huan-Neng Chen ,  William Wu Shen ,  Chewn-Pu Jou ,  Feng Wei Kuo ,  Lan-Chou Cho ,  Tze-Chiang Huang ,  Jack Liu ,  Yun-Han Lee

IPC: H04L12/28 ,  H04L5/14 ,  H04W52/02

Abstract: An integrated circuit includes a first radio frequency interconnect (RFI) transceiver, a second RFI transceiver, a third RFI transceiver, a fourth RFI transceiver and a guided transmission medium. The first RFI transceiver is configured to transmit or receive a first data signal. The second RFI transceiver is configured to transmit or receive a second data signal. The third RFI transceiver is configured to transmit or receive the first data signal. The fourth RFI transceiver is configured to transmit or receive the second data signal. The guided transmission medium is configured to carry the first data signal and the second data signal. The first RFI transceiver and the second RFI transceiver are connected to the third RFI transceiver and the fourth RFI transceiver by the guided transmission medium.

公开(公告)号：US09835680B2

公开(公告)日：2017-12-05

申请号：US14659064

申请日：2015-03-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Sandeep Kumar Goel ,  Yun-Han Lee ,  Saman M. I. Adham

IPC: G01R31/28 ,  G01R31/30 ,  G01R31/3183

CPC classification number: G01R31/3008 ,  G01R31/318307

Abstract: A method performed at least partially by a processor includes performing a test sequence. In the test sequence, a test pattern is loaded into a circuit. The test pattern is configured to cause the circuit to output a predetermined test response. A test response is unloaded from the circuit after a test wait time period has passed since the loading of the test pattern into the circuit. The unloaded test response is compared with the predetermined test response.

公开(公告)号：US20170300607A1

公开(公告)日：2017-10-19

申请号：US15641024

申请日：2017-07-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yun-Han Lee ,  Wu-An Kuo

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row.

公开(公告)号：US09633147B1

公开(公告)日：2017-04-25

申请号：US14874881

申请日：2015-10-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Stanley John ,  Sandeep Kumar Goel ,  Tze-Chiang Huang ,  Yun-Han Lee

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/5036 ,  G06F17/5045 ,  G06F2217/78

Abstract: In some embodiments, in a method performed by at least one processor for estimating an overall power state coverage of an electronic system level (ESL) model comprising a plurality of blocks for a module, a first value and a second value are set for each block of said plurality of blocks. At least one verification case is selected for each block in the ESL model. For each verification case of said at least one verification case: (a) a target coverage value is set, (b) a register transfer level (RTL) simulation is performed, (c) an actual coverage value is received, and (d) the first value or the second value is updated based on whether the actual coverage value is less than the target coverage value or not. A power state coverage is calculated for said each block. The overall power state coverage is calculated for the ESL model comprising said plurality of blocks for said module.

公开(公告)号：US20160364331A1

公开(公告)日：2016-12-15

申请号：US15248093

申请日：2016-08-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsien-Hsin Sean Lee ,  William Wu Shen ,  Yun-Han Lee

IPC: G06F12/0804 ,  G06F12/0891 ,  G11C7/22

Abstract: A method of operating a memory circuit is disclosed. The memory circuit comprises a primary memory and a cache memory. The primary memory has P access channels of Q bits of channel bandwidth, and the cache memory has P subsets of Q*N memory cells, wherein P and Q are integers greater than 1, and N is a positive integer. The method includes determining, in response to a command for reading first and second data accessible through first and second access channels respectively, if a valid duplication of the first and second data is stored in the cache memory. If yes, the method further includes storing a duplication of Q*n bits of consecutively addressed data from each of the first and second access channels to the cache memory, n being an integer from 1 to N. Otherwise, the method further includes outputting the first and second data from the cache memory.

Abstract translation: 公开了一种操作存储器电路的方法。 存储器电路包括主存储器和高速缓冲存储器。 主存储器具有信道带宽Q位的P个访问信道，高速缓冲存储器具有Q * N个存储单元的P个子集，其中P和Q是大于1的整数，N是正整数。 该方法包括响应于用于分别读取通过第一和第二访问信道访问的第一和第二数据的命令，确定第一和第二数据的有效复制是否存储在高速缓冲存储器中。 如果是，则该方法还包括将来自第一和第二访问信道中的每一个的连续寻址数据的Q * n位的复制存储到高速缓存存储器，n是从1到N的整数。否则，该方法还包括：输出 来自高速缓冲存储器的第一和第二数据。

公开(公告)号：US09406597B2

公开(公告)日：2016-08-02

申请号：US14228986

申请日：2014-03-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shyh-An Chi ,  Mark Shane Peng ,  Yun-Han Lee

IPC: H01L23/50 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H01L23/48

CPC classification number: H01L23/49811 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/50 ,  H01L24/48 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit system comprises an interposer, a first integrated circuit, and at least one voltage regulator module. The first integrated circuit comprises first bond pads, and is electrically connected to the interposer at a first position of the interposer via the first bond pads. The first integrated circuit also comprises second bond pads. The first integrated circuit further comprises at least two circuit blocks. The at least two circuit blocks are configured to operate at different operating voltages. The at least one voltage regulator module is electrically connected to the first integrated circuit via the second bond pads, and the at least one voltage regulator module is configured to convert a received power supply voltage to the respective operating voltage of one of the at least two circuit blocks and supply the respective operating voltage via the second bond pads.

Abstract translation: 集成电路系统包括插入器，第一集成电路和至少一个电压调节器模块。 第一集成电路包括第一接合焊盘，并且经由第一接合焊盘在插入器的第一位置处电连接到插入器。 第一集成电路还包括第二接合焊盘。 第一集成电路还包括至少两个电路块。 至少两个电路块被配置为在不同的工作电压下工作。 所述至少一个电压调节器模块经由所述第二接合焊盘电连接到所述第一集成电路，并且所述至少一个电压调节器模块被配置为将接收到的电源电压转换为所述至少两个 电路块，并通过第二接合焊盘提供相应的工作电压。