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    Mechanisms for built-in self test and repair for memory devices
    1.
    发明授权
    Mechanisms for built-in self test and repair for memory devices 有权
    用于内存自检和修复内存设备的机制

    公开(公告)号：US09269459B2

    公开(公告)日：2016-02-23

    申请号：US14585726

    申请日：2014-12-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Saman M. I. Adham ,  Chao-Jung Hung

    IPC: G11C29/00 ,  G11C29/44 ,  G11C17/14 ,  G11C17/16

    CPC classification number: G11C29/4401 ,  G11C17/146 ,  G11C17/16 ,  G11C29/785 ,  G11C2029/4402

    Abstract: A method of storing repair data of a memory array in a one-time programming memory (OTPM) includes performing a first test and repair of the memory array using a built-in self-test-and-repair (BISTR) module to determine first repair data. The method includes loading the first repair data in a repair memory and in a duplicated repair memory of the BISTR module. The method includes performing a second test and repair to determine second repair data. The method includes storing the second repair data in the repair memory of the BISTR module and in the repair memory of the memory array. The method includes processing the repair data in the repair memory and the duplicated repair memory of the BISTR module. The method includes storing the output of the logic gate in the repair memory of the memory array. The method includes storing content of the repair memory in the OTPM.

    Abstract translation: 一种将一个存储器阵列的修复数据存储在一次性编程存储器（OTPM）中的方法包括使用内置的自检和修复（BISTR）模块执行存储器阵列的第一次测试和修复，以确定第一 修复数据。 该方法包括将第一修复数据加载到BISTR模块的修复存储器和复制修复存储器中。 该方法包括执行第二次测试和修复以确定第二修复数据。 该方法包括将第二修复数据存储在BISTR模块的修复存储器和存储器阵列的修复存储器中。 该方法包括处理修复存储器中的修复数据和BISTR模块的重复修复存储器。 该方法包括将逻辑门的输出存储在存储器阵列的修复存储器中。 该方法包括将修复存储器的内容存储在OTPM中。

    Fault injection of finFET devices
    6.
    发明授权
    Fault injection of finFET devices 有权
    finFET器件的故障注入

    公开(公告)号：US08959468B2

    公开(公告)日：2015-02-17

    申请号：US13864725

    申请日：2013-04-17

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Atul Katoch ,  Saman M. I. Adham ,  Cormac Michael O'Connell

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5036

    Abstract: Defect-describing (or “cut”) layer(s) for describing defects associated with different sides of a 3-dimensional (3D) structure enable fault modeling to determine the effect of position and location of defects on transistor performance. One or more defect-describing layers are used to identify the coordinates and sides of the 3D structures of the defects. The defect-describing layer(s) enables fault-modeling for 3D structures to understand the effects of faults on different locations, especially for defects associated with the fins of the finFET devices. Faults are injected to different locations and sides of fins and are modeled with different test vectors, test parameters and testing devices to identify detectable faults. The fault modeling would help identify the sources of defects and also improve layout design of finFET device structures.

    Abstract translation: 用于描述与三维（3D）结构的不同侧相关的缺陷的缺陷描述（或“切割”）层使故障建模能够确定缺陷的位置和位置对晶体管性能的影响。 使用一个或多个缺陷描述层来识别缺陷的3D结构的坐标和侧面。 缺陷描述层使得能够对3D结构进行故障建模，以了解故障对不同位置的影响，特别是对于与finFET器件的翅片相关的缺陷。 故障被注入散热片的不同位置和侧面，并用不同的测试向量，测试参数和测试设备建模，以识别可检测的故障。 故障建模将有助于识别缺陷的来源，并改善finFET器件结构的布局设计。

    Mechanisms for built-in self repair of memory devices using failed bit maps and obvious repairs
    7.
    发明授权
    Mechanisms for built-in self repair of memory devices using failed bit maps and obvious repairs 有权
    使用故障位图和明显修复的内存设备内置自修复机制

    公开(公告)号：US08760949B2

    公开(公告)日：2014-06-24

    申请号：US13942040

    申请日：2013-07-15

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Volodymyr Shvydun ,  Saman M. I. Adham

    IPC: G11C7/00

    CPC classification number: G11C29/4401 ,  G11C29/72 ,  G11C2029/0401 ,  G11C2029/4402

    Abstract: A method of self-testing and self-repairing a random access memory (RAM) is includes collecting failure data of the RAM with redundant rows and columns, wherein the failure data of all failed cells of the RAM are stored in two failure bit map (FBM) data structures. The method further includes performing obvious repair of failed cells during the collecting of the failure data and analyzing the failure data in the two FBM data structure to determine repair methods. The method further includes repairing failed cells of the RAM by using the redundant rows and columns.

    Abstract translation: 随机存取存储器（RAM）的自检和自修复的方法包括以冗余行和列收集RAM的故障数据，其中RAM的所有故障单元的故障数据存储在两个故障位图中 FBM）数据结构。 该方法还包括在收集故障数据期间执行故障小区的明显修复，并分析两个FBM数据结构中的故障数据以确定修复方法。 该方法还包括通过使用冗余行和列来修复RAM的故障单元。

    Fault injection of finFET devices
    10.
    发明授权
    Fault injection of finFET devices 有权
    finFET器件的故障注入

    公开(公告)号：US09367662B2

    公开(公告)日：2016-06-14

    申请号：US14605485

    申请日：2015-01-26

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Atul Katoch ,  Saman M. I. Adham ,  Cormac Michael O'Connell

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5036

    Abstract: A device layout tool includes a gate electrode layer, wherein the gate electrode layer is configured to define a three dimensional gate structure over a fin structure, wherein the fin structure has three exposed surfaces. The device layout tool further includes a defect-describing layer, wherein the defect-describing layer is configured to define locations of gate defects relative to the three exposed surfaces of the fin structure.

    Abstract translation: 器件布局工具包括栅极电极层，其中栅电极层被配置为在翅片结构上限定三维栅极结构，其中鳍结构具有三个暴露表面。 所述设备布局工具还包括缺陷描述层，其中所述缺陷描述层被配置为限定相对于所述鳍结构的三个暴露表面的栅极缺陷的位置。

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